Numerous embodiments are disclosed of a non-volatile memory cell array formed in a p-well, which is formed in a deep n-well, which is formed in a p-substrate. During an erase operation, a negative voltage is applied to the p-well, which reduces the peak positive voltage required to be applied to the cells to cause the cells to erase.

A method of forming a device on a substrate with recessed first/third areas relative to a second area by forming a fin in the second area, forming first source/drain regions (with first channel region therebetween) by first/second implantations, forming second source/drain regions in the third area (defining second channel region therebetween) by the second implantation, forming third source/drain regions in the fin (defining third channel region therebetween) by third implantation, forming a floating gate over a first portion of the first channel region by first polysilicon deposition, forming a control gate over the floating gate by second polysilicon deposition, forming an erase gate over the first source region and a device gate over the second channel region by third polysilicon deposition, and forming a word line gate over a second portion of the first channel region and a logic gate over the third channel region by metal deposition.

A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.

A semiconductor structure for a memory device includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer, and the first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the firs dopant concentration.

In a method of manufacturing a semiconductor device, a memory cell structure covered by a protective layer is formed in a memory cell area of a substrate. A mask pattern is formed. The mask pattern has an opening over a first circuit area, while the memory cell area and a second circuit area are covered by the mask pattern. The substrate in the first circuit area is recessed, while the memory cell area and the second circuit area are protected. A first field effect transistor (FET) having a first gate dielectric layer is formed in the first circuit area over the recessed substrate and a second FET having a second gate dielectric layer is formed in the second circuit area over the substrate as viewed in cross section.

An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

A semiconductor device includes a peripheral circuit structure; a lower stack disposed on the peripheral circuit structure and an upper stack disposed in the lower stack including a plurality of lower insulating layers and a plurality of lower word lines alternately stacked with the lower insulating layers; a plurality of channel structures extending through the lower stack and the upper stack in the cell array area; a pair of separation insulating layers extending vertically through the lower stack and the upper stack and extending in a horizontal direction, the pair of separation insulating layers being spaced apart from each other in a vertical direction; and a word line separation layer disposed at an upper portion of the lower stack and crossing the pair of separation insulating layers when viewed in a plan view, the word line separation layer extending vertically through at least one of the lower word lines.

A manufacturing method of a non-volatile memory device, includes forming a floating gate on a substrate, depositing a first insulating layer on the floating gate, depositing a second insulating layer on the first insulating layer, depositing a third insulating layer on the second insulating layer, performing a first etch-back process on the third insulating layer to form a spacer-shaped third insulating layer on the second insulating layer, performing a second etch-back process on the second insulating layer to form a spacer-shaped second insulating layer on the first insulating layer, and performing a wet etching to remove the spacer-shaped third insulating layer to form a spacer-shaped first insulating layer and the spacer-shaped second insulating layer on the floating gate.

The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same. In one aspect, a method of fabricating a semiconductor device comprises: a) providing a substrate and a first hardmask; b) next, providing a second hardmask over a first region of the first hardmask; c) next, forming a first set of hardmask fins in a second region of the first hardmask; d) next, masking the second region; e) next, providing a set of photoresist fins on the second hardmask; f) next, patterning the second hardmask and the first region by using the photoresist fins as a mask; g) next, forming a first set of semiconductor fins of a first height by etching the substrate; h) next, removing the mask provided in step d; i) next, forming a second set of semiconductor fins of a second height in the second region and extending the height of the first set of semiconductor fins to a third height in the first region, by etching the substrate by using the first and second sets of hardmask fins as masks.

A non-volatile semiconductor memory and three or more types of transistors are provided. A thickness of a first gate oxide film of a first transistor is larger than that of a second gate oxide film of a second transistor, and is smaller than that of a third gate oxide film of a third transistor. In a first transistor region, a first silicon oxide film is formed on a surface of a semiconductor substrate, and second and third silicon oxide films are formed on the first silicon oxide film. By removing the second and third silicon oxide films and a part of an upper layer of the first silicon oxide film, the first gate oxide film is formed from the first silicon oxide film.