The present disclosure pertains to the field of carbon nanotube technologies, and provides a carbon nanotube semiconductor device and a manufacturing method thereof. The manufacturing method of a carbon nanotube semiconductor device provided in the present disclosure comprises: forming a carbon nanotube layer with a carbon nanotube solution; and treating the carbon nanotube layer with an acidic solution. The carbon nanotube semiconductor device manufactured by the method of the present disclosure has good performance uniformity.

A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

A negative differential resistance device includes a dielectric layer having a first surface and a second surface opposing the first surface, a first semiconductor layer that includes a first degenerated layer that is on the first surface of the dielectric layer and has a first polarity, a second semiconductor layer that includes a second degenerated layer that has a region that overlaps the first semiconductor layer and has a second polarity, a first electrode electrically connected to the first semiconductor layer, a second electrode electrically connected to the second semiconductor layer, and a third electrode on the second surface of the dielectric layer and which has a region overlapping at least one of the first semiconductor layer or the second semiconductor layer.

The present application relates to a self-assembled monolayer suitable for the modification of electrodes comprised in electronic devices as well as to such electronic devices. The present application also relates to a method for depositing such self-assembled monolayer onto an electrode as well as to the manufacturing of the corresponding devices.

In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure including CNTs embedded in a semiconductor layer is formed, a sacrificial gate structure is formed over the fin structure, the semiconductor layer is doped at a source/drain region of the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, and a source/drain contact layer is formed over the doped source/drain region of the fin structure.

We describe a method for reducing a parasitic resistance at an interface between a conducting electrode region and an organic semiconductor in a thin film transistor, the method comprising: providing a solution comprising a dopant for doping said semiconductor, and depositing said solution onto said semiconductor and/or said conducting electrode region to selectively dope said semiconductor adjacent said interface between said conducting electrode region and said semiconductor, wherein depositing said solution comprises inkjet-printing said solution.

Provided are a transparent conductive laminate, a transparent electrode including the transparent conductive laminate, and a manufacturing method for the transparent conductive laminate.

A carbon nanotube composite has an organic substance attached to at least a part of a surface thereof. At least one functional group selected from a hydroxyl group, a carboxy group, an amino group, a mercapto group, a sulfo group, a phosphonic acid group, an organic or inorganic salt thereof, a formyl group, a maleimide group and a succinimide group is contained in at least a part of the carbon nanotube composite.

An organic thin film transistor (OTFT) is disclosed herein. The OTFT has a substrate, a data line, a transfer pad, a source electrode, a drain electrode, an active pattern, a first insulating layer, a gate electrode, a second insulating layer, and a transparent electrode. The data line and the transfer pad are disposed on the substrate. The source electrode and the drain electrode are disposed on the substrate, the data line, and the transfer pad. The active pattern is disposed on the data line, the transfer pad, the substrate, the source electrode, and the drain electrode. With the disposition of the active pattern on the source electrode and the drain electrode, the source electrode and the drain electrode are free from the bombardment of the plasma.

A thin film transistor array includes thin film transistors positioned in a matrix, each of the thin film transistors including a substrate, a gate electrode formed on the substrate, a gate insulation layer formed on the gate electrode, a source electrode formed on the gate insulation layer, a drain electrode formed on the gate insulation layer, a pixel electrode formed on the gate insulation layer and connected to the source electrode and the drain electrode, a semiconductor layer formed between the source electrode and the drain electrode, an interlayer insulation film covering the source electrode, the drain electrode, the semiconductor layer and a portion of the pixel electrode, and an upper pixel electrode formed on the interlayer insulation film and connected to the pixel electrode. The interlayer insulation film has one or more concave portions and one or more via hole portions.