Patent classifications
H10K10/86
Thin film transistor
A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.
Thin film transistor
A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a carbon nanotube structure.
Memristive device based on tunable schottky barrier
Memristive devices based on tunable Schottky barrier are provided. In one aspect, a method of forming a memristive device includes: forming a semiconductor layer on a bottom metal electrode, wherein the semiconductor layer has workfunction-modifying molecules embedded therein; and forming a top metal electrode on the semiconductor layer, wherein the top metal electrode forms a Schottky junction with the semiconductor layer, and wherein the workfunction-modifying molecules are configured to alter a workfunction of the top metal electrode. A memristive device and a method for operating a memristive device are also provided.
CARBON NANOTUBE ARRAY
A carbon nanotube array with equal or other ratio of semiconductive to conductive elements in integrated form including: a plurality of carbon nanotubes arranged in an array, wherein each carbon nanotube includes a semiconducting carbon nanotube segment and a metallic carbon nanotube segment, and the semiconducting carbon nanotube segment and the metallic carbon nanotube segment are connected with each other.
Memristive Device Based on Tunable Schottky Barrier
Memristive devices based on tunable Schottky barrier are provided. In one aspect, a method of forming a memristive device includes: forming a semiconductor layer on a bottom metal electrode, wherein the semiconductor layer has workfunction-modifying molecules embedded therein; and forming a top metal electrode on the semiconductor layer, wherein the top metal electrode forms a Schottky junction with the semiconductor layer, and wherein the workfunction-modifying molecules are configured to alter a workfunction of the top metal electrode. A memristive device and a method for operating a memristive device are also provided.
THIN FILM TRANSISTOR
A thin film transistor includes a gate, an insulating medium layer and a Schottky diode. The Schottky diode includes a first electrode, a second electrode and a semiconducting structure. The first electrode is located on the surface of the insulating medium layer and includes a first metal layer and a second metal layer. The second electrode is located on the surface of the insulating medium layer and includes a third metal layer and a fourth metal layer. The semiconductor structure includes a first end and a second end. The first end is sandwiched by the first metal layer and the second metal layer, the second end is sandwiched by the third metal layer and the fourth metal layer. The semiconductor structure includes a carbon nanotube structure.
THIN FILM TRANSISTOR
A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a nano-scale semiconductor structure. The second electrode is located on the second end.
THIN FILM TRANSISTOR
A thin film transistor includes a gate electrode, a insulating medium layer and at least one Schottky diode unit. The at least one Schottky diode unit is located on a surface of the insulating medium layer. The at least one Schottky diode unit includes a first electrode, a semiconductor structure and a second electrode. The semiconductor structure comprising a first end and a second end. The first end is laid on the first electrode, the second end is located on the surface of the insulating medium layer. The semiconducting structure includes a carbon nanotube structure. The second electrode is located on the second end.
Ambipolar vertical field effect transistor
Various examples are provided for ambipolar vertical field effect transistors (VFETs). In one example, among others, an ambipolar VFET includes a gate layer; a source layer that is electrically percolating and perforated; a dielectric layer; a drain layer; and a semiconducting channel layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric layer and the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier. Another example includes an ambipolar vertical field effect transistor including a dielectric surface treatment layer. The semiconducting channel layer is in contact with at least a portion of the source layer and at least a portion of the dielectric surface treatment layer and where the source layer and the semiconducting channel layer form a gate voltage tunable charge injection barrier.