According to various implementations of the invention, a vertical Josephson Junction device may be realized using molecular beam epitaxy (MBE) growth of YBCO and PBCO epitaxial layers in an a-axis crystal orientation. Various implementations of the invention provide improved vertical JJ devices using SiC or LSGO substrates; GaN, AlN, or MgO buffer layers; YBCO or LSGO template layers; YBCO conductive layers and various combinations of barrier layers that include PBCO, NBCO, and DBCO. Such JJ devices are simple to fabricate with wet and dry etching, and allow for superior current flow across the barrier layers.

Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.

This disclosure relates to fabrication of step edges to fabricate Josephson junctions. A method comprises forming a layer of resist over the surface. The layer of resist comprises openings to expose a selected area of the surface, thereby forming two walls in the layer of resist on a perimeter of the selected area. The resist and the substrate are exposed to an ion beam, thereby etching the resist and the exposed areas of the surface. While exposing the resist and the substrate to the ion beam, the substrate is gradually rotated about an axis normal to the surface to thereby form two step edges at the respective two walls. Further, superconducting material is deposited onto the substrate in a meandering shape to form a path that crosses the two step edges multiple times and to form a Josephson junction each time the path crosses the step edges.

This disclosure relates to Superconducting Quantum Interference Apparatuses, such as SQUID arrays and SQUIFs. A superconducting quantum interference apparatus comprises an array of loops each loop constituting a superconducting quantum interference device. The array comprises multiple columns, each of the columns comprises multiple rows connected in series, each of the multiple rows comprises a number of loops connected in parallel, and the number of loops connected in parallel in each row is more than two and less than 20 to improve a performance of the apparatus. It is an advantage that keeping the number of loops in parallel below 20 improves the performance of the apparatus. This is contrary to existing knowledge where it is commonly assumed that a larger number of parallel loops would increase performance.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a “braided” pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

A device includes a plurality of superconducting components, each having a first terminal and a second terminal; a plurality of current sources, being electrically-connected to the first terminal of a corresponding superconducting component and configured to selectively provide a first current; and a bias current source electrically-connected to the respective first terminal of each of the plurality of superconducting components. The bias current source is configured to provide a second current adapted to bias the superconducting components such that (1) a combination of the second current and the first current from each current source causes the plurality of superconducting components to transition from the superconducting state to the non-superconducting state, and (2) a combination of the second current and the first current from each current source of only a subset of the plurality of current sources does not cause the plurality of superconducting components to transition to the non-superconducting state.

This disclosure relates to fabrication of step edges to fabricate Josephson junctions. A method comprises forming a layer of resist over the surface. The layer of resist comprises openings to expose a selected area of the surface, thereby forming two walls in the layer of resist on a perimeter of the selected area. The resist and the substrate are exposed to an ion beam, thereby etching the resist and the exposed areas of the surface. While exposing the resist and the substrate to the ion beam, the substrate is gradually rotated about an axis normal to the surface to thereby form two step edges at the respective two walls. Further, superconducting material is deposited onto the substrate in a meandering shape to form a path that crosses the two step edges multiple times and to form a Josephson junction each time the path crosses the step edges.

This disclosure relates to Superconducting Quantum Interference Apparatuses, such as SQUID arrays and SQUIFs. A superconducting quantum interference apparatus comprises an array of loops each loop constituting a superconducting quantum interference device. The array comprises multiple columns, each of the columns comprises multiple rows connected in series, each of the multiple rows comprises a number of loops connected in parallel, and the number of loops connected in parallel in each row is more than two and less than 20 to improve a performance of the apparatus. It is an advantage that keeping the number of loops in parallel below 20 improves the performance of the apparatus. This is contrary to existing knowledge where it is commonly assumed that a larger number of parallel loops would increase performance.

Approaches useful to operation of scalable processors with ever larger numbers of logic devices (e.g., qubits) advantageously take advantage of QFPs, for example to implement shift registers, multiplexers (i.e., MUXs), de-multiplexers (i.e., DEMUXs), and permanent magnetic memories (i.e., PMMs), and the like, and/or employ XY or XYZ addressing schemes, and/or employ control lines that extend in a braided pattern across an array of devices. Many of these described approaches are particularly suited for implementing input to and/or output from such processors. Superconducting quantum processors comprising superconducting digital-analog converters (DACs) are provided. The DACs may use kinetic inductance to store energy via thin-film superconducting materials and/or series of Josephson junctions, and may use single-loop or multi-loop designs. Particular constructions of energy storage elements are disclosed, including meandering structures. Galvanic connections between DACs and/or with target devices are disclosed, as well as inductive connections.

A superconducting medium includes a first layer made of a first superconductor and a second layer made of a second superconductor. The first layer has a first thickness less than a first coherence length of the first superconductor. The second layer has a second thickness less than a second coherence length of the second superconductor so as to induce a proximity effect between the first layer and the second layer. The proximity effect can induce desirable properties in the resulting superconducting medium. Controlling the thickness ratio of the first layer to the second layer can also tune the property of the superconducting medium.