H10N60/124

Magnetic flux-to-voltage transducer based on josephson junction arrays

A device and method for converting magnetic flux to voltage uses a Fraunhofer pattern of a 1D array of long Josephson junctions. The 1D array of Josephson junctions may include from 1 to 10.sup.9 junctions formed in a planar geometry with a bridge width within the range of 4-10 m.

Nanowire-based superconducting electrostrictive device

A Josephson junction device and methods for manufacture can include an untwinned YBa.sub.2Cu.sub.3O.sub.x nanowire having crystallographic a- and b-axes. The nanowire can be established from YBa.sub.2Cu.sub.3O.sub.x film (6.0x7.0) using a photolithography process, followed by an ion milling process, to yield the YBa.sub.2Cu.sub.3O.sub.x nanowire. The crystallographic b-axis of the nanowire can be parallel to the long dimension of the nanowire. First and second gate structures can be placed on opposite sides of the nanowire across from each other, to establish first and second microgaps. A gate voltage can be selectively applied across the first and said second gate structures, which can further establish a selective electric field across the first and second microgaps. The electric field can be parallel to the nanowire crystallographic a-axis, to selectively cause an at will Josephson junction effect.

Electrical, mechanical, computing, and/or other devices formed of extremely low resistance materials

Electrical, mechanical, computing, and/or other devices that include components formed of extremely low resistance (ELR) materials, including, but not limited to, modified ELR materials, layered ELR materials, and new ELR materials, are described.

Thermal management for superconducting interconnects

An interconnect may have a first end coupled to a superconducting system and a second end coupled to a non-superconducting system. The interconnect may include a superconducting element having a critical temperature. During operation of the superconducting system and the non-superconducting system, a first portion of the interconnect near the first end may have a first temperature equal to or below the critical temperature of the superconducting element, a second portion of the interconnect near the second end may have a second temperature above the critical temperature of the superconducting element, and the interconnect may further be configured to reduce a length of the second portion such that temperature substantially over an entire length of the interconnect is maintained at a temperature equal to or below the critical temperature of the superconducting element.

THERMAL MANAGEMENT FOR SUPERCONDUCTING INTERCONNECTS
20180294401 · 2018-10-11 ·

An interconnect may have a first end coupled to a superconducting system and a second end coupled to a non-superconducting system. The interconnect may include a superconducting element having a critical temperature. During operation of the superconducting system and the non-superconducting system, a first portion of the interconnect near the first end may have a first temperature equal to or below the critical temperature of the superconducting element, a second portion of the interconnect near the second end may have a second temperature above the critical temperature of the superconducting element, and the interconnect may further be configured to reduce a length of the second portion such that temperature substantially over an entire length of the interconnect is maintained at a temperature equal to or below the critical temperature of the superconducting element.

Superconducting logic circuits
12095462 · 2024-09-17 · ·

An electric circuit includes one or more photon detector components and a superconducting logic gate component coupled to respective outputs of the one or more photon detector components. The electric circuit further includes a bias source electrically coupled to the superconducting logic gate component, the bias source configured to provide a bias current adapted to cause the superconducting logic gate component to function as a logical gate. The electric circuit also includes an optical switch component electrically coupled to an output of the superconducting logic gate component.

SYSTEMS AND METHODS FOR HYBRID SUPERCONDUCTING MEDIUM
20180248103 · 2018-08-30 ·

A superconducting medium includes a first layer made of a first superconductor and a second layer made of a second superconductor. The first layer has a first thickness less than a first coherence length of the first superconductor. The second layer has a second thickness less than a second coherence length of the second superconductor so as to induce a proximity effect between the first layer and the second layer. The proximity effect can induce desirable properties in the resulting superconducting medium. Controlling the thickness ratio of the first layer to the second layer can also tune the property of the superconducting medium.

HIGH TEMPERATURE SUPERCONDUCTING DEVICES AND METHODS THEREOF
20240389476 · 2024-11-21 ·

A high temperature superconducting device including a substrate, a high temperature superconducting thin film disposed on the substrate and one or more non-superconducting thin film regions formed adjacent to and across a substantially entire thickness of the high temperature superconducting thin film. In the high temperature superconducting device, the one or more non-superconducting thin film regions are formed from degrading corresponding superconducting materials same to the high temperature superconducting thin film through applying an external voltage. In addition, the one or more non-superconducting thin film regions and the high temperature superconducting thin film form one or more Josephson tunnel junctions.

CONTACT LAYER FOR LAYERED MATERIALS

An electronics device comprises a substrate, a first layer of a first layered material arranged over the substrate, a second layer of a second layered material arranged over the substrate, an overlap region, and a contact layer. In the overlap region, the second layer is arranged over the first layer, and a section of a bottom surface of the second layer is parallel to a section of a top surface of the first layer. The contact layer comprises a plurality of electrically conductive lines and an electrical insulation element. The plurality of electrically conductive lines comprises a first electrically conductive line and a second electrically conductive line. The first electrically conductive line and/or the second electrically conductive line comprises a superconductor material.

QUBIT DEVICE, METHOD FOR FABRICATING THE QUBIT DEVICE, AND CONTACT LAYER FOR THE METHOD
20250008844 · 2025-01-02 ·

A qubit device comprises first and second superconductor layers a capacitor, first and second interconnects. The first superconductor layer comprises a first c-axis perpendicular to covalently bound atomic layers. The second superconductor layer comprises a second c-axis perpendicular to covalently bound atomic layers. The first and second superconductor layers form a Josephson junction, wherein the first c-axis and the second c-axis are aligned with each other at the Josephson junction. The aligned first and second c-axes intersect both the first superconductor layer and the second superconductor layer. The capacitor comprises a first electrode and a second electrode. The first interconnect electrically connects the first electrode and the first superconductor layer. The second interconnect electrically connects the second electrode and the second superconductor layer. The capacitor is arranged at a vertical position exceeding the vertical positions of both the first superconductor layer and the second superconductor layer.