The method that includes the step of a cleaning a surface of a silicon wafer and forming a sacrificial layer on top of the silicon wafer. The wafer undergoes further processing, wherein the processing includes forming at least one layer directly on top of the sacrificial layer. Immediately prior to the insertion into a dilute refrigeration unit removing a portion of the sacrificial layer by exposing the portion of the sacrificial layer to a solvent.

A superconducting device according to an example embodiment includes: a superconducting chip; an interposer on which the superconducting chip is mounted; a socket that is arranged to face the interposer and includes a movable pin and a housing supporting the movable pin; and a board that is arranged to face the socket and includes a connector serving as an input/output with respect to the outside. In the board, one end of a terminal of a via hole is electrically connected to one end of a terminal of the movable pin, and a hole diameter of the via hole is smaller than a diameter of a tip portion of the movable pin connected to the via hole.

The invention relates to a method for forming flip chip bumps using electroplating. The method allows the formation of flip chip bumps in a way that is compatible with already-formed sensitive electronic components, such as Josephson junctions, which may be used in quantum processing units. The invention also relates to a product and a flip chip package in which flip chip bumps are formed with the disclosed method.

A quantum computing system that includes a quantum circuit device having at least one operating frequency; a first substrate having a first surface on which the quantum circuit device is disposed; a second substrate having a first surface that defines a recess of the second substrate, the first and second substrates being arranged such that the recess of the second substrate forms an enclosure that houses the quantum circuit device; and an electrically conducting layer that covers at least a portion of the recess of the second substrate.

A quantum computing device is formed using a first chip and a second chip, the first chip having a first substrate, a first set of pads, and a set of Josephson junctions disposed on the first substrate. The second chip has a second substrate, a second set of pads disposed on the second substrate opposite the first set of pads, and a second layer formed on a subset of the second set of pads. The second layer is configured to bond the first chip and the second chip. The subset of the second set of pads corresponds to a subset of the set of Josephson junctions selected to avoid frequency collision between qubits in a set of qubits. A qubit is formed using a Josephson junction from the subset of Josephson junctions and another Josephson junction not in the subset being rendered unusable for forming qubits.

The present disclosure relates to routing superconducting wires in superconducting circuits and in particular to efficiently routing superconducting wires that meet inductance requirements. The superconducting wire routing technique involves modeling the target location not only as a physical location, but as a physical location (e.g., x, y, and z dimensions) combined with inductance (e.g., a target inductance range). One or more other constraints may also be included in the modeling, such as a number of wires that would need to be moved/lifted, a number of circuit-vias allowing passage through layers of the circuit, an amount of cross-coupling with other inductors, and a number of wire segments.

A quantum device according to an example embodiment includes: a quantum chip with a first surface and a second surface located on a side opposite to the first surface, in the quantum chip, at least a part of a qubit circuit being provided on the second surface; a first interposer with a third surface and a fourth surface located on a side opposite to the third surface, the first interposer being connected to the quantum chip in such a manner that the second surface of the quantum chip is opposed to the third surface of the first interposer; and a second interposer with a fifth surface and a sixth surface located on a side opposite to the fifth surface, the second interposer being connected to the first interposer in such a manner that the fourth surface of the first interpose is opposed to the fifth surface of the second interposer.

The present disclosure provides an ion implantation method and an ion implanter for realizing the ion implantation method. The above-mentioned ion implantation method comprises: providing a spot-shaped ion beam current implanted into the wafer; controlling the wafer to move back and forth in a first direction; controlling the spot-shaped ion beam current to scan back and forth in a second direction perpendicular to the first direction; and adjusting the scanning width of the spot-shaped ion beam current in the second direction according to the width of the portion of the wafer currently scanned by the spot-shaped ion beam current in the second direction. According to the ion implantation method provided by the present disclosure, the scanning path of the ion beam current is adjusted by changing the scanning width of the ion beam current, so that the beam scanning area is attached to the wafer, which greatly reduces the waste of the ion beam current, improves the effective ion beam current and increases productivity without increasing actual ion beam current.

Devices and methods that can facilitate vertical dispersive readout of qubits of a lattice surface code architecture are provided. According to an embodiment, a device can comprise a first substrate that can have a first side and a second side that can be opposite the first side. The first substrate can comprise a read pad that can be located on the first side and a readout resonator that can be located on the second side. The device can further comprise a second substrate that can be connected to the first substrate. The second substrate can comprise a qubit. In some embodiments, the device can further comprise a recess that can be located on the first side of the first substrate. The recess can comprise the read pad.

Devices, systems, methods, computer-implemented methods, apparatus, and/or computer program products that can facilitate an epitaxial Josephson junction transmon device are provided. According to an embodiment, a device can comprise a substrate. The device can further comprise an epitaxial Josephson junction transmon device coupled to the substrate. According to an embodiment, a device can comprise an epitaxial Josephson junction transmon device coupled to a substrate. The device can further comprise a tuning gate coupled to the substrate and formed across the epitaxial Josephson junction transmon device. According to an embodiment, a device can comprise a first superconducting region and a second superconducting region formed on a substrate. The device can further comprise an epitaxial Josephson junction tunneling channel coupled to the first superconducting region and the second superconducting region.