There is described a cable for carrying electrical current in a coil of a magnet. The cable comprises a stack of tape assemblies, each tape assembly comprising a high-strength metal substrate layer, and an HTS layer of high temperature superconductor material. The tape assemblies are stacked as a series of type 0 pairs such that the HTS layers of a type 0 pair face each other and the substrate layers of the type 0 pair are separated by the HTS layers.

The present invention provides for polycrystalline superconducting permanent magnets which are synthesized of doped superconducting (AE) Fe.sub.2As.sub.2 compounds, where AE denotes an alkaline earth metal, such as Ba, Sr, Mg or Ca. The superconducting permanent magnets of the present invention can be magnetized in their superconducting state by induced currents, resulting in trapped magnetization that scales with the size of the bulk material. The magnitude of the trapped field has been demonstrated to be over 1 T and is predicted to be over 10 T if the technology is scaled, which is much higher than the capabilities of permanent magnets and other superconducting polycrystalline bulks currently known in the art.

Provided is a niobium-zirconium (NbZr) alloy comprising an ordered body-centered cubic (bcc) ?-NbZr phase, methods for making the same, a superconducting radio-frequency (SRF) cavity surface comprising the NbZr alloy, a particle accelerator wherein an SRF cavity comprising the NbZr alloy, a superconductor-insulator-superconductor tunnel junction (SIS) wherein a first superconductor/electrode and the second superconductor/electrode comprise the NbZr alloy, and a quantum computer or quantum computing device comprising an SRF cavity or a resonator wherein at least a portion of at least one surface of the SRF cavity or resonator comprising the NbZr alloy. The NbZr alloy, e.g., produced under ambient conditions, comprises less than or equal to 50 at. % Zr and yields critical temperatures up to, e.g., 16.5 K.

The present invention relates to a precursor (1) for production of a high-temperature superconductor (HTS) in ribbon form, comprising a metallic substrate (10) in ribbon form having a first ribbon side (11) and a second ribbon side (12), wherein, on the first ribbon side (11), (a) the substrate (10) has a defined texture as template for crystallographically aligned growth of a buffer layer or an HTS layer and (b) an exposed surface of the substrate (10) is present or one or more layers (20,30) are present that are selected from the group consisting of: buffer precursor layer, pyrolyzed buffer precursor layer, buffer layer, HTS precursor layer, pyrolyzed HTS buffer precursor layer and pyrolyzed and further consolidated HTS buffer precursor layer, and, on the second ribbon side (12), at least one ceramic barrier layer (40) that protects the substrate (10) against oxidation or a precursor which is converted to such a layer during the HTS crystallization annealing or the pyrolysis is present, wherein, when one or more layers (20, 30) are present on the first ribbon side (11), the ceramic barrier layer (40) or the precursor thereof has a different chemical composition and/or a different texture than the layer (20) arranged on the first ribbon side (11) and directly adjoining the substrate (10). In this precursor, the barrier layer (40) is a layer that delays or prevents ingress of oxygen to the second ribbon side (12) and is composed of conductive ceramic material or a precursor which is converted to such a precursor during the HTS crystallization annealing or the pyrolysis, and the ceramic material is an electrically conductive metal oxide or an electrically conductive mixture of metal oxides, wherein the conductive metal oxide or one or more metal oxides in the conductive mixture is/are preferably metal oxide(s) doped with an extraneous metal.

The present disclosure relates to nanoscale device comprising an elongated crystalline nanostructure, such as a nanowire crystal, a nanowhisker crystal or a nanorod crystal, and a method for producing thereof. One embodiment relates to a nanoscale device comprising an elongated crystalline semiconductor nanostructure, such as a nanowire (crystal) or nanowhisker (crystal) or nanorod (crystal), having a plurality of substantially plane side facets, a crystalline structured first facet layer of a superconductor material covering at least a part of one or more of said side facets, and a second facet layer of a superconductor material covering at least a part of the first facet layer, the superconductor material of the second facet layer being different from the superconductor material of the first facet layer, wherein the crystalline structure of the semiconductor nanostructure is epitaxially matched with the crystalline structure of the first facet layer on the interface between the two crystalline structures.

Vertically integrated superconductor/semiconductor heterostructures that comprise the necessary components of a quantum computer, which could enable integrated on-chip quantum computing at millikelvin temperatures, are disclosed.

A photon-number-resolving detector comprises a detection element, an ohmmeter, and a hardware logic component. The detection element can be formed from a Weyl or Dirac semimetal. Electrons of the detection element are characterized by a surface state that exhibits a Dirac cone and a bulk superconducting state that exhibits a bandgap. When photons having energies less than the bandgap of the bulk superconducting state impinges on the detection element, the photons can be absorbed by electrons of the detection element that are characterized by the surface state. The ohmmeter outputs resistance data indicative of an electrical resistance of the detection element while the photons impinge on the detection element. The hardware logic component can determine, based upon the resistance data, a number of the photons that are absorbed by the surface state electrons of the detection element.

High density resistive memory structures, integrate circuits with high density resistive memory structures, and methods for fabricating high density resistive memory structures are provided. In an embodiment, a high density resistive memory structure includes a semiconductor substrate and a plurality of first electrodes in a first plane in and/or over the semiconductor substrate. Further, the high density resistive memory structure includes a plurality of second electrodes in a second plane in and/or over the semiconductor substrate. The second plane is parallel to the first plane, and each second electrode in the plurality of second electrodes crosses over or under each first electrode in the plurality of first electrodes at a series of cross points. Each second electrode in the plurality of second electrodes is non-linear and the series of cross points formed by each respective second electrode is non-linear.

A lid or other chamber component for a process chamber comprises a) at least one surface comprising a first ceramic material, wherein the first ceramic material comprises Y.sub.3Al.sub.5O.sub.12 and b) an internal region beneath the at least one surface comprising a second ceramic material, wherein the second ceramic material comprises a combination of Al.sub.2O.sub.3 and ZrO.sub.2.

The present disclosure relates to semiconductor based Josephson junctions and their applications within the field of quantum computing, in particular a tuneable Josephson junction device has been used to construct a gateable transmon qubit. One embodiment relates to a Josephson junction comprising an elongated hybrid nanostructure comprising superconductor and semiconductor materials and a weak link, wherein the weak link is formed by a semiconductor segment of the elongated hybrid nanostructure wherein the superconductor material has been removed to provide a semiconductor weak link.