The present invention provides a multi-layer selector device exhibiting a low leakage current by controlling a threshold voltage. According to an embodiment of the present invention, the multi-layer selector device comprises: a substrate; a lower electrode layer disposed on the substrate; an insulating layer disposed on the lower electrode layer and having a via hole passing through to expose the lower electrode layer; a switching layer disposed on the lower electrode layer in the via hole, performing a switching operation by forming and destroying a conductive filament, and made of a multi-layer to control the formation of the conductive filament; and an upper electrode layer disposed on the switching layer.

A method is presented for reducing element segregation of a phase change material (PCM). The method includes forming a bottom electrode, constructing a layered stack over the bottom electrode, the layered stack including the PCM separated by one or more electrically conductive and chemically stable materials, and forming a top electrode over the layered stack. The PCM is Ge—Sb—Te (germanium-antimony-tellurium or GST) and the one or more electrically conductive and chemically stable materials are titanium nitride (TiN) segments.

The present disclosure relates to resistive random-access memory (RRAM) devices. In some embodiments, a RRAM device may include a first electrode; a second electrode comprising an alloy containing tantalum; and a switching oxide layer positioned between the first electrode and the second electrode, wherein the switching oxide layer includes at least one transition metal oxide. The alloy containing tantalum may further contain at least one of hafnium, molybdenum, tungsten, niobium, or zirconium. In some embodiments, the alloy containing tantalum may include one or more of a binary alloy containing tantalum, a ternary alloy containing tantalum, a quaternary alloy containing tantalum, a quinary alloy containing tantalum, a senary alloy containing tantalum, and a high order alloy containing tantalum.

A memory device structure includes a first electrode, a second electrode, a switching layer between the first electrode and the second electrode, where the switching layer is to transition between first and second resistive states at a voltage threshold. The memory device further includes an oxygen exchange layer between the switching layer and the second electrode, where the oxygen exchange layer includes a metal and a sidewall oxide in contact with a sidewall of the oxygen exchange layer. The sidewall oxide includes the metal of the oxygen exchange layer and oxygen, and has a lateral thickness that exceed a thickness of the switching layer.

A method is presented for reducing element segregation of a phase change material (PCM). The method includes forming a bottom electrode, constructing a layered stack over the bottom electrode, the layered stack including the PCM separated by one or more electrically conductive and chemically stable materials, and forming a top electrode over the layered stack. The PCM is Ge—Sb—Te (germanium-antimony-tellurium or GST) and the one or more electrically conductive and chemically stable materials are titanium nitride (TiN) segments.

Methods, systems, and devices for techniques for forming memory structures are described. Forming a memory structure may include etching a stack of material including a conductive line, a first electrode and a sacrificial material to divide the stack of material into multiple sections. The process may further include depositing an oxide material in each of the first quantity of channels to form multiple oxide materials. The sacrificial material may be etched to form a second channel between two oxide materials of the multiple oxide materials. Memory material may be deposited over the two oxide materials and the second channel, which may create a void in the second channel between the memory material and the first electrode. The memory material may be heated to fill the void in the second channel.

Switching oxide engineering technologies relating to low current RRAM-based crossbar array circuits are disclosed. An apparatus, in some implementations, includes: a substrate; a bottom electrode formed on the substrate; a switching oxide stack formed on the bottom electrode. The switching oxide stack includes one or more base oxide layers and one or more discontinuous oxide layers alternately stacked; An apparatus further includes a top electrode formed on the switching oxide stack. The base oxide layer includes TaO.sub.x, HfO.sub.x, TiO.sub.x, ZrO.sub.x, or a combination thereof. The discontinuous oxide layer includes Al.sub.2O.sub.3, SiO.sub.2, Si.sub.3N.sub.4, Y.sub.2O.sub.3, Gd.sub.2O.sub.3, Sm.sub.2O.sub.3, CeO.sub.2, Er.sub.2O.sub.3, or the combination thereof.

A memory includes: a first electrode comprising a top boundary and a sidewall; a resistive material layer, disposed above the first electrode, that comprises at least a first portion and a second portion coupled to a first end of the first portion, wherein the resistive material layer presents a variable resistance value; and a second electrode disposed above the resistive material layer.

A preparation method of a silicon-based molecular beam heteroepitaxy material, a memristor, and use thereof are provided. A structure of the heteroepitaxy material is obtained by allowing a SrTiO.sub.3 layer, a La.sub.0.67Sr.sub.0.33MnO.sub.3 layer, and a (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 layer to successively grow on a P-type Si substrate. The silicon-based epitaxy structure is obtained by allowing a first layer of SrTiO.sub.3, a second layer of La.sub.0.67Sr.sub.0.33MnO.sub.3, and a third layer of (BaTiO.sub.3).sub.0.5—(CeO.sub.2).sub.0.5 (in which an atomic ratio of BaTiO.sub.3 to CeO.sub.2 is 0.5:0.5) to successively grow at a specific temperature and a specific oxygen pressure. The preparation method of a silicon-based molecular beam heteroepitaxy material adopts pulsed laser deposition (PLD), which is relatively simple and easy to control, and can achieve the memristor function and neuro-imitation characteristics. A thickness of the first buffer layer of SrTiO.sub.3 can reach 40 nm.

A method for manufacturing an OxRAM type resistive memory cell including a silicon oxide layer, the method including determining manufacturing parameter values enabling the resistive memory cell to have an initial resistance between 10.sup.7Ω and 3.Math.10.sup.9Ω; and forming on a substrate a stack successively including a first electrode, the silicon oxide layer and a second electrode, by applying the manufacturing parameter values.