The present invention provides methods to sputter deposit films comprising alkali metal compounds. At least one target comprising one or more alkali metal compounds and at least one metallic component is sputtered to form one or more corresponding sputtered films. The at least one target has an atomic ratio of the alkali metal compound to the at least one metallic component in the range from 15:85 to 85:15. The sputtered film(s) incorporating such alkali metal compounds are incorporated into a precursor structure also comprising one or more chalcogenide precursor films. The precursor structure is heated in the presence of at least one chalcogen to form a chalcogenide semiconductor. The resultant chalcogenide semiconductor comprises up to 2 atomic percent of alkali metal content, wherein at least a major portion of the alkali metal content of the resultant chalcogenide semiconductor is derived from the sputtered film(s) incorporating the alkali metal compound(s). The chalcogenide semiconductors are useful in microelectronic devices, including solar cells.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

Provided are a conductive bridging random access memory (CBRAM) device and a manufacturing method thereof. The CBRAM device includes a first electrode, a semiconductor oxide electrolyte layer formed on the first electrode and including a plurality of metal vacancies, a second electrode formed on the semiconductor oxide electrolyte layer, wherein when a positive voltage is applied to the second electrode, cations are reduced to the metal vacancies in the semiconductor oxide electrolyte layer to form a metal bridge.

A method for fabricating a semiconductor device includes forming air gaps within respective dielectric layer portions to reduce thermal cross-talk between adjacent bits. Each of the dielectric portions is formed on a substrate each adjacent to sidewall liners formed on sidewalls of a phase change memory (PCM) layer. The method further includes forming a pillar including the sidewall liners and the PCM layer, and forming a selector layer on the pillar and the dielectric portions.

A structure including a bottom electrode, a phase change material layer, the phase change material layer includes a similar lattice constant as a lattice constant of the substrate, a top electrode on and vertically aligned with the phase change material layer, a dielectric material horizontally isolating the bottom electrode from the top electrode and the phase change material layer. A structure including a phase change material layer selected from amorphous silicon, amorphous germanium and amorphous silicon germanium, a top electrode on the phase change material layer, a bottom electrode, a dielectric material isolating the bottom electrode from the top electrode and the phase change material layer. Forming a bottom electrode, forming a phase change material layer adjacent to the bottom electrode, forming a top electrode above the phase change material, forming a dielectric material horizontally isolating the bottom electrode from the top electrode and the phase change material layer.

A method of using memristor aided logic (MAGIC), comprises connecting together two input and one output memristor between a bit line and a word line, each memristor having a high resistance state and a low resistance state, setting the output memristor to the low resistance state as an initiation state and then applying logic inputs to the input memristors. The output then depends on whether the logic inputs have set the output memristor to the high resistance state.

A method for manufacturing a resistive device, includes depositing a first electrically conductive layer on a substrate; forming an etching mask on the first conductive layer; etching the first conductive layer through the mask, such as to obtain a plurality of electrically conductive pillars separated from one another; and forming storage elements with variable electrical resistance at the tops of the electrically conductive pillars, such that each storage element is supported by one of the electrically conductive pillars, the step of forming the storage elements including the following operations depositing a first layer by non-collimated cathode sputtering at normal incidence relative to the substrate; and depositing a second layer on the first layer by cathode sputtering, the second layer including a first chemical species sputtered at an oblique incidence.

The objective of the present invention is to make it possible to manufacture, with a high yield, a metal deposition type variable-resistance element with which variability of a program voltage and a leakage current under a high resistance state is reduced, while the program voltage is reduced. This variable-resistance element comprises: a first electrode which is embedded in a first insulating film and which supplies metal ions, an upper surface of the first electrode being exposed out of the first insulating film by means of an opening portion in a second insulating film covering the first insulating film; a metal deposition type variable-resistance film which covers the opening portion and is in contact with the upper surface of the first electrode; and a second electrode in contact with the upper surface of the variable-resistance film. The width of the opening portion is greater than the width of the upper surface of the first electrode, and the edge portions of the opening portion are provided in such a way that there is a margin between the edge portions of the opening portion and the edge portions of the upper surface of the first electrode which face the edge portions of the opening portion.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric filed to cause oxygen ionic motion.

A plurality of memory cells in a cross-point array with improved endurance is disclosed. Each memory cell, disposed between first and second conductors, includes a switch in series with a pillar of phase change material. The pillar has a Te-rich material at one end proximal to the second conductor, and an Sb-rich material at the other end proximal to the first conductor, wherein the current direction is from the first conductor to the second conductor.