A memory device includes: a memory layer that is isolated for each memory cell and stores information by a variation of a resistance value; an ion source layer that is formed to be isolated for each memory cell and to be laminated on the memory layer, and contains at least one kind of element selected from Cu, Ag, Zn, Al and Zr and at least one kind of element selected from Te, S and Se; an insulation layer that isolates the memory layer and the ion source layer for each memory cell; and a diffusion preventing barrier that is provided at a periphery of the memory layer and the ion source layer of each memory cell to prevent the diffusion of the element.

A RRAM and a method for fabricating the same, wherein the RRAM comprises: a bottom electrode; an oxide layer containing a bottom electrode metal, disposed on the bottom electrode; a resistance-switching layer, disposed on the oxide layer containing a bottom electrode metal, wherein the resistance-switching layer material is a nitrogen-containing tantalum oxide; an inserting layer, disposed on the resistance-switching layer, wherein the inserting layer material comprises a metal or a semiconductor; a top electrode, disposed on the inserting layer. By providing the to resistance-switching layer with a nitrogen-containing tantalum oxide, compared with Ta.sub.2O.sub.5, the RRAM of the present disclosure has a low activation voltage and a high on-off ratio, and can enhance the control capability over the device resistance by the number of oxygen vacancies.

A switching element includes a lower barrier electrode on a substrate, a switching pattern on the lower barrier electrode, and an upper barrier electrode on the switching pattern. The lower barrier electrode includes a first lower barrier electrode layer, and a second lower barrier electrode layer interposed between the first lower barrier electrode layer and the switching pattern and whose density is different from the density of the first lower barrier electrode.

Phase change memory cells, structures, and devices having a phase change material and an electrode forming an ohmic contact therewith are disclosed and described. Such electrodes can have a resistivity of from 10 to 100 mOhm.Math.cm.

Disclosed herein are metal filament memory cells, and related devices and techniques. In some embodiments, a memory cell may include: a transistor having a source/drain region; and a metal filament memory device including an active metal and an electrolyte; wherein the electrolyte is coupled between the active metal and the source/drain region when the transistor is an n-type metal oxide semiconductor (NMOS) transistor, and the active metal is coupled between the electrolyte and the source/drain region when the transistor is a p-type metal oxide semiconductor (PMOS) transistor.

A memory device includes a bottom electrode above a substrate, a first switching layer on the bottom electrode, a second switching layer including aluminum on the first switching layer, an oxygen exchange layer on the second switching layer and a top electrode on the oxygen exchange layer. The presence of the second switching layer including aluminum on the first switching layer enables a reduction in electro-forming voltage of the memory device.

In one embodiment, a capacitor-like structure is constructed that includes an RF co-sputtered TMO layer. The capacitor-like structure includes a first electrode (e.g., a bottom electrode) constructed of a first metal (e.g., Pt), a RF co-sputtered TMO layer on the first electrode including a first oxide and a second oxide (e.g., a RF co-sputtered Al.sub.2O.sub.3—NiO layer), and a second electrode constructed of a second metal (e.g., Pt) in contact with the co-sputtered TMO layer. The capacitor-like structure is resistively switchable due to formation and rupture of CFs through the RF co-sputtered TMO layer in response to application of a voltage between the first electrode and the second electrode. The RF co-sputtered TMO layer may be grown using at least one direct oxide target (e.g., a NiO target) in a noble gas (e.g., Ar) atmosphere.

Various embodiments of the present disclosure are directed towards a memory device including a data storage structure overlying a substrate. A bottom electrode overlies the substrate and a top electrode overlies the bottom electrode. The data storage structure is disposed between the bottom electrode and the top electrode. The data storage structure comprises a dielectric material doped with a first dopant and a second dopant, where the first dopant is different from the second dopant.

A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.