A semiconductor device includes a first level having a plurality of transistor devices, and a first wiring level positioned over the first level. The first wiring level includes a plurality of conductive lines extending parallel to the first level, and one or more programmable horizontal bridges extending parallel to the first level. Each of the one or more programmable horizontal bridges electrically connects two respective conductive lines of the plurality of conductive lines in the first wiring level. The one or more programmable horizontal bridges include a programmable material having a modifiable resistivity in that the one or more programmable horizontal bridges change between being conductive and being non-conductive.

According to one embodiment, a nonvolatile memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction, a third wiring extending in the second direction and spaced from the second wiring in the first direction. An insulating layer includes a first portion between the second wiring and the third wiring, and a second portion protruding from the first portion in a third direction. A chalcogenide layer is between the first wiring and the second wiring, the first wiring and the third wiring, and also the first wiring and the insulating layer. The chalcogenide layer includes a first layer portion, a second layer portion, and a third layer portion. A concentration of a first element in the third layer portion is higher than that in the first and second layer portions.

A phase-change material having specific SiO.sub.x doping into special Ge-rich Ge.sub.xSb.sub.yTe.sub.z material is described. Integrated circuits using this phase-change material as memory elements in a memory array can pass the solder bonding criteria mentioned above, while exhibiting good set speeds and demonstrating good 10 year data retention characteristics. A memory cell described herein comprises a first electrode and a second electrode; and a memory element in electrical series between the first and second electrode. The memory element comprises a Ge.sub.xSb.sub.yTe.sub.z phase change material with a silicon oxide additive, including a combination of elements having Ge in a range of 28 to 36 at %, Sb in a range of 10 to 20 at %, Te in a range of 25 to 40 at %, Si in a range of 5 to 10 at %, and O in a range of 12 to 23 at %.

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

In a method for forming a semiconductor device, a plurality of conductive lines is formed as a part of a first wiring level of the semiconductor device. The first wiring level is positioned over a first level having a plurality of transistor devices. The plurality of conductive lines extends parallel to the first level. In addition, a programmable horizontal bridge is formed that extends parallel to the first level, and electrically connects a first conductive line and a second conductive line of the plurality of conductive lines in the first wiring level. The programmable horizontal bridge is formed based on a programmable material that changes phase between a conductive state and a non-conductive state according to a current pattern delivered to the programmable horizontal bridge.

An electronic device including a semiconductor memory is provided. The semiconductor memory may include memory elements. Each of the memory elements comprises: a selection element layer in which a first dopant is doped in an insulating material; and a variable resistance layer in which a second dopant is doped in the insulating material. A diffusivity of the second dopant in the insulating material is greater than a diffusivity of the first dopant in the insulating material.

According to one embodiment, a method of manufacturing a memory device including a silicon oxide and a variable resistance element electrically coupled to the silicon oxide, includes: introducing a dopant into the silicon oxide from a first surface of the silicon oxide by ion implantation; and etching the first surface of the silicon oxide with an ion beam.

An electronic device including a semiconductor memory is provided. The semiconductor memory may include memory elements. Each of the memory elements comprises: a selection element layer in which a first dopant is doped in an insulating material; and a variable resistance layer in which a second dopant is doped in the insulating material. A diffusivity of the second dopant in the insulating material is greater than a diffusivity of the first dopant in the insulating material.

A memory cell including a two-terminal re-writeable non-volatile memory element having at least two layers of conductive metal oxide (CMO), which, in turn, can include a first layer of CMO including mobile oxygen ions, and a second layer of CMO formed in contact with the first layer of CMO to cooperate with the first layer of CMO to form an ion obstruction barrier. The ion obstruction barrier is configured to inhibit transport or diffusion of a subset of mobile ion to enhance, among other things, memory effects and cycling endurance of memory cells. At least one layer of an insulating metal oxide that is an electrolyte to the mobile oxygen ions and configured as a tunnel barrier is formed in contact with the second layer of CMO.

A method for manufacturing a resistive random access memory includes depositing a layer made of an active material of variable electrical resistance on a substrate containing a first electrode, forming a lower electrode; depositing an electrically conductive layer on the active material layer; etching the electrically conductive layer so as to delimit a second electrode, forming an upper electrode, facing the lower electrode; exposing at least one flank of the upper electrode to an ion beam inclined with respect to the normal to the substrate by an angle (α) comprised between 20° and 65°, so as to implant the ions in a portion of the active material layer adjacent to the flank and located under the upper electrode, the ion implantation conditions being chosen so as to create defects in the structure of the active material and to obtain an average implantation width comprised between 5 nm and 10 nm.