A non-volatile memory device and a semiconductor structure including a vertical resistive memory cell and a fabrication method therefor. The semiconductor structure including a target metal contact; a horizontal dielectric layer; and at least one vertically oriented memory cell, each vertically oriented memory cell including a vertical memory resistive element having top and bottom electrical contacts, and including a vertically-oriented seam including conductive material and extending vertically from, and electrically connected to, the bottom electrical contact, the vertically-oriented seam and the bottom electrical contact entirely located in the horizontal dielectric layer; and one of the top and bottom electrical contacts being electrically connected to the target metal contact. The target electrical contact can be electrically connected to a memory cell selector device.

Memory cells and methods of forming and operating the same include forming a doped crystalline semiconductor memory layer on a first electrode. The doped crystalline semiconductor memory layer has a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer. A second electrode is formed on the doped crystalline semiconductor memory layer.

Resistive RAM (RRAM) devices having increased reliability and related manufacturing methods are described in combination with stacked technology with CMOS ASIC wafters. Greater reliability of RRAM cells over time can be achieved by avoiding direct contact of metal electrodes with the device switching layer. Stacking technology can be used to address incompatibility of ReRAM processing and CMOS ASICs processing.

A semiconductor storage device includes at least a first electrode layer including a first material; and a memory layer including a second material having a high-resistance state and a low-resistance state switchable based on electric heating. The memory layer has a side surface covered by a side wall layer, the side wall layer including a third material with a higher melting temperature than the second material. The first material has an amorphous structure, a thermal conductivity at least 2-digits lower than a thermal conductivity of a single phase metal, and a resistivity equal to or lower than 50 mΩ.Math.cm and a positive temperature dependence.

An resistive random-access memory (RRAM) device including an first crystalline semiconductor layer disposed adjacent to a crystalline semiconductor substrate, a crystal lattice edge-dislocation segment disposed at an interface of the first crystalline semiconductor layer and crystalline semiconductor substrate, the lattice edge-dislocation segment including first and second segment ends, a first ion-source electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the first segment end of the lattice edge-dislocation segment, and a second electrode disposed upon the electrically isolating spacer, adjacent to the crystalline substrate and first crystalline semiconductor layer, and further disposed in contact with the second segment end of the lattice edge-dislocation segment.

Methods for adjusting a work function of a structure in a substrate leverage near surface doping. In some embodiments, a method for adjusting a work function of a structure in a substrate may include growing an epitaxial layer on surfaces of the structure to form a homogeneous passivation region as part of a substrate material of the substrate and performing a dopant diffusion process to further embed the dopants into surfaces of the structure to adjust a work function of the structure, wherein the dopant diffusion process is performed at less than approximately 450 degrees Celsius.

Memory cells and methods of forming and operating the same include forming a doped crystalline semiconductor memory layer on a first electrode. The doped crystalline semiconductor memory layer has a programmable dopant activation level that determines a resistance of the doped crystalline semiconductor memory layer. A second electrode is formed on the doped crystalline semiconductor memory layer.

Provided is a microswitch including a first electrode, a second electrode, and a porous coordination polymer conductor, in which the porous coordination polymer conductor is represented by the following Formula (1), and a metal forming the first electrode and a metal forming the second electrode have different oxidation-reduction potentials,
[ML.sub.x].sub.n(D).sub.y  (1), where M represents a metal ion selected from group 2 to group 13 elements in a periodic table, L represents a ligand that has two or more functional groups capable of coordination to M in a structure of L and is crosslinkable with two M's, D represents a conductivity aid that includes no metal element, x represents 0.5 to 4 and y represents 0.0001 to 20 with respect to x as 1, n represents the number of repeating units of a constituent unit represented by [ML.sub.x], and n represents 5 or more.

A physical unclonable functions (PUF) device including a first copper electrode, a second electrode, and a silicon oxide layer positioned directly between the first copper electrode and the second electrode; a method of producing a PUF device; an array comprising a PUF device; and a method of generating a secure key with a plurality of PUF devices.

The present disclosure discloses a resistive random access memory, and the resistive random access memory includes a lower electrode layer, a ferroelectric material layer, and an upper electrode layer arranged in sequence from bottom to top, wherein the ferroelectric material layer includes a doped HfO.sub.2 ferroelectric thin film.