A memory cell includes a bottom electrode, a first dielectric layer, a variable resistance layer, and a top electrode. The first dielectric layer laterally surrounds the bottom electrode. A top surface of the bottom electrode is located at a level height lower than that of a top surface of the first dielectric layer. The variable resistance layer is disposed on the bottom electrode and the first dielectric layer. The variable resistance layer contacts the top surface of the bottom electrode and the top surface of the first dielectric layer. The top electrode is disposed on the variable resistance layer.

A ReRAM device includes a dielectric layer, a bottom electrode, a data storage layer, a metal covering layer, and a top electrode. The dielectric layer has a recess. At least a portion of the bottom electrode is exposed through the recess. The data storage layer is disposed on a sidewall and a bottom surface of the recess, electrically contacts with the bottom electrode, and has a top portion lower than an opening of the recess. The metal covering layer blanket covers the data storage layer, has an extension portion covering the top portion, and connects to the sidewall of the recess. The top electrode is disposed in the recess, and is electrically contact with the metal covering layer.

An object of the present invention is to provide a composition, a memory structure suitable for the composition, a manufacturing method, and an operating method for stable operation in a memory element including a chalcogen compound. In order to achieve the object, in a memory array with a cross-point structure including a first electrode line and a second electrode line intersecting each other, and a selective memory element disposed at each intersection of the first electrode line and the second electrode line and being a chalcogen compound, the present invention may provide the memory array with a cross-point structure including the first electrode line formed on a substrate, a first functional electrode formed between the first electrode line and the selective memory element, and a second functional electrode formed between the second electrode line and the selective memory element, wherein the first functional electrode is formed as a line along the first electrode line.

The present invention provides a multi-layer selector device exhibiting a low leakage current by controlling a threshold voltage. According to an embodiment of the present invention, the multi-layer selector device comprises: a substrate; a lower electrode layer disposed on the substrate; an insulating layer disposed on the lower electrode layer and having a via hole passing through to expose the lower electrode layer; a switching layer disposed on the lower electrode layer in the via hole, performing a switching operation by forming and destroying a conductive filament, and made of a multi-layer to control the formation of the conductive filament; and an upper electrode layer disposed on the switching layer.

A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

A three-dimensional semiconductor integrated circuit includes a first CMOS circuit layer including a plurality of first CMOS circuit blocks; an insulating layer disposed on a top of the first CMOS circuit layer; a plurality of atomic switching elements respectively disposed inside via holes extending through the insulating layer, wherein the plurality of atomic switching elements are electrically connected to the plurality of first CMOS circuit blocks, respectively; a driver circuit layer disposed on a top of the insulating layer, and electrically connected with the atomic switching elements, wherein the driver circuit layer include a driver circuit for selectively turning on and off the atomic switching elements; and a second CMOS circuit disposed on a top of the driver circuit layer and connected to the atomic switching elements.

A memory device and method of forming the same are provided. The memory device includes a first memory cell disposed over a substrate. The first memory cell includes a transistor and a data storage structure coupled to the transistor. The transistor includes a gate pillar structure, a channel layer laterally wrapping around the gate pillar structure, a source electrode surrounding the channel layer, and a drain electrode surrounding the channel layer. The drain electrode is separated from the source electrode a dielectric layer therebetween. The data storage structure includes a data storage layer surrounding the channel layer and sandwiched between a first electrode and a second electrode. The drain electrode of the transistor and the first electrode of the data storage structure share a common conductive layer.

A memory device includes a bottom electrode, a selector, a memory layer, and a top electrode. The selector is over the bottom electrode. A sidewall of the bottom electrode and a sidewall of the selector are coterminous. The memory layer is formed over the selector and has a width greater than a width of the selector. A top electrode is formed over the memory layer.

A phase change memory device based on a nano current channel is provided. A nano current channel layer structure is adopted and configured to limit the current channel. As such, when flowing through the layer, the current enters the phase change layer from nano crystal grains with high electrical conductivity, and the current is thereby confined in the nano current channels. By using the nano-scale conductive channels, the contact area between the phase change layer and the electrode layer is significantly decreased, the current density at local contact channel is significantly increased, and heat generation efficiency of the current in the phase change layer is improved. Moreover, an electrically insulating and heat-insulating material with low electrical conductivity and low thermal conductivity prevents heat in the phase change layer from being dissipated to the electrode layer, and Joule heat utilization efficiency of the phase change layer is thereby improved.

An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.