A memory device according to one embodiment includes a resistance change film, an insulating film provided on the resistance change film, a first wiring provided on the insulating film and being not in contact with the resistance change film, and a high resistance film having a higher resistivity than the first wiring. The high resistance film is provided on a side surface of a stacked body including the insulating film and the first wiring, and the high resistance film is electrically connected between the first wiring and the resistance change film.

A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.

A memory using mixed valence conductive oxides is disclosed. The memory includes a mixed valence conductive oxide that is less conductive in its oxygen deficient state and a mixed electronic ionic conductor that is an electrolyte to oxygen and promotes an electric field effective to cause oxygen ionic motion.

A method of forming a disturb-resistant non volatile memory device includes providing a substrate and forming a first dielectric thereon, forming a first strip of material separated from a second strip of material from a first wiring material, and forming a second dielectric thereon to fill a gap between the first and second strips of material. Openings are formed in the second dielectric exposing portions of the first wiring material. Filing the openings by p+ polysilicon contact material, and then an undoped amorphous silicon material, and then a metal material. A second wiring structure is formed thereon to contact the metal material in the openings. Resistive switching cells are formed from the first wiring structure, the second wiring structure, the contact material, the undoped amorphous silicon material, and the metal material.

Provided are a conductive bridging random access memory (CBRAM) device and a manufacturing method thereof. The CBRAM device includes a first electrode, a semiconductor oxide electrolyte layer formed on the first electrode and including a plurality of metal vacancies, a second electrode formed on the semiconductor oxide electrolyte layer, wherein when a positive voltage is applied to the second electrode, cations are reduced to the metal vacancies in the semiconductor oxide electrolyte layer to form a metal bridge.

A semiconductor device includes a bottom electrode, a top electrode over the bottom electrode, a switching layer between the bottom electrode and the top electrode, wherein the switching layer is configured to store data, a capping layer in contact with the switching layer, wherein the capping layer is configured to extract active metal ions from the switching layer, an ion reservoir region formed in the capping layer, a diffusion barrier layer between the bottom electrode and the switching layer, wherein the diffusion barrier layer includes palladium (Pd), cobalt (Co), or a combination thereof and is configured to obstruct diffusion of the active metal ions between the switching layer and the bottom electrode, and the diffusion layer has a concaved top surface, and a passivation layer covering a portion of the top electrode, and wherein the passivation layer directly contacts a top surface of the switching layer.

Lateral programmable metallization cells may comprise a solid electrolyte layer, an anode coupled to the solid electrolyte layer, and a cathode coupled to the solid electrolyte layer. Exemplary solid electrolyte layers may comprise a first layer comprising an oxide electrolyte and a copper species and a second layer comprising at least one copper species, the second layer coupled to the first layer.

A three-terminal synaptic device includes a substrate; a source electrode and a drain electrode which are provided on the substrate and spaced apart from each other. The three-terminal synaptic device further includes: a channel layer provided on the substrate, the source electrode, and the drain electrode; an ion reservoir layer which stores active ions; a gate electrode provided on the ion reservoir layer; and an ion barrier layer disposed between the ion reservoir layer. In particular, the channel layer controls movement of active ions between the ion reservoir layer and the channel layer. The three-terminal synaptic device inhibits rapid movement of ions.

A switch device includes a first electrode, a second electrode, and a switch layer. The second electrode is disposed to face the first electrode. The switch layer is provided between the first electrode and the second electrode. The switch layer contains an amorphous material made of at least germanium (Ge) and one of nitrogen (N) and oxygen (O).

A resistive random access memory overcomes the low durability of the conventional resistive random access memory. The resistive random access memory includes a first electrode, a second electrode, an enclosing layer and an oxygen-containing resistance changing layer. The first and second electrodes are separate from each other. The enclosing layer forms a first via-hole. The oxygen-containing resistance changing layer is arranged for the first via-hole. The first and second electrodes and the enclosing layer jointly enclose the oxygen-containing resistance changing layer. Each of the first electrode, the second electrode and the enclosing layer is made of an element not containing oxygen.