The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.

A method includes providing a semiconductor substrate comprising a main surface, forming a dielectric region on the main surface, forming a recess in the dielectric region, forming a strip of phase change material within the recess, forming a heating element that is thermally coupled to the strip of phase change material, forming an interconnection region over the main surface before or after forming the recess, the interconnection region including a metallization layer and a dielectric layer, electrically connecting the strip of phase change material to a connecting one of the metallization layers from the interconnection region, and completing formation of the interconnection region after electrically connecting the strip of phase change material, wherein completing formation of the interconnection region includes forming an outer one of the dielectric layers from the interconnection region that is disposed over the connecting one of the metallization layers and comprises a planar upper surface.

A semiconductor memory device designed to mitigate degradation due to heat, and methods of forming such a device, are described. In one example, a memory cell in a memory device includes an insulating layer formed over a substrate, a horizontal crossbar electrode formed over the insulating layer, a metal oxide resistive memory layer formed over the horizontal crossbar electrode, and a vertical crossbar electrode formed over the resistive switching memory layer. In one aspect of the embodiments, the horizontal crossbar electrode includes a thermally conductive horizontal crossbar layer formed over the insulating layer and a platinum horizontal crossbar electrode formed over the thermally conductive horizontal crossbar layer. The thermally conductive horizontal crossbar layer can be a layer of copper for thermal dissipation of heat away from the memory cell during set and reset operations, reducing degradation in the memory device.

Memory devices and methods of forming the same are provided. A memory device includes a substrate, a first conductive layer, a phase change layer, a selector layer and a second conductive layer. The first conductive layer is disposed over the substrate. The phase change layer is disposed over the first conductive layer. The selector layer is disposed between the phase change layer and the first conductive layer. The second conductive layer is disposed over the phase change layer. In some embodiments, at least one of the phase change layer and the selector layer has a narrow-middle profile.

A phase change memory cell for a semiconductor device that includes a heater element on a first conductive layer with a spacer surrounding sides of the heater element. The phase change memory cell includes a first dielectric layer on the conductive layer and on a bottom portion of the spacer surrounding the heater element and a second dielectric layer on the first dielectric layer surrounding a top portion of the heater element. The phase change memory cell includes a phase change material on a top surface of the heater element and on the second dielectric material.

A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.

An approach to form a semiconductor structure with a multiple layer phase change material stack and four electrodes that functions as an integrated switch device. The semiconductor structure includes a sidewall spacer that is on two opposing sides of the multiple layer phase change material stack contacting an edge of each layer of the multiple layer phase change material stack. The semiconductor structure includes a pair of a first type of electrode, where each of the pair of the first type of electrode abuts each of the sidewall spacers on the two opposing sides of the multiple layer phase change material stack. A pair of a second type of electrode, where each of the second type of electrode abuts each of two other opposing sides of the multiple layer phase change material stack and contacts a heater material on outside portions of the multiple layer phase change material stack.

A memory array with memory cells may have one or more heaters integrated into the memory array between the memory cells. A processor in communication with the heater may notify the heater to activate when a trigger event occurs.

A resistive random-access memory (ReRAM) device may include a thermally engineered layer that is positioned adjacent to an active layer and configured to act as a heat sink during filament formation in response to applied voltages. The thermally engineered layer may act as one of the electrodes on the ReRAM device and may be adjacent to any side of the active layer. The active layer may also include a plurality of individual active layers. Each of the active layers may be associated with a different dielectric constant, such that the middle active layer has a dielectric constant that is significantly higher than the other two surrounding active layers.

A method is presented for reducing a reset current for a phase change memory (PCM). The method includes forming a bottom electrode, constructing a PCM cell structure including a plurality of phase change memory layers and a plurality of heat transfer layers, wherein the plurality of phase change memory layers are assembled in an alternating configuration with respect to the plurality of heat transfer layers, and forming a top electrode over the PCM cell structure. The plurality of phase change memory layers are arranged perpendicular to the top and bottom electrodes. Additionally, airgaps are defined adjacent the PCM cell structure.