The present invention is directed to a varistor comprising a dielectric material comprising a sintered ceramic composed of zinc oxide grains and a grain boundary layer between the zinc oxide grains. The grain boundary layer contains a positive temperature coefficient thermistor material in an amount of less than 10 mol % based on the grain boundary layer.

A positive temperature coefficient (PTC) heater is disclosed. In an embodiment the PTC heater includes a main body having a length L, a width B, and a height H made of a PTC material and a first electrode and a second electrode made of an electrically conductive material, wherein the following is true for L, B, and H: LBH, and wherein the electrodes are connected to the main body so that the following is true for a spacing d thereof from one another: d>H.

The present invention is directed to a varistor comprising a dielectric material comprising a sintered ceramic composed of zinc oxide grains and a grain boundary layer between the zinc oxide grains. The grain boundary layer contains a positive temperature coefficient thermistor material in an amount of less than 10 mol % based on the grain boundary layer.

A PTC thermistor element for a tempering device may include a main body, which may have a positive temperature coefficient. The main body may have PTC thermistor components, a core, and ceramics components at least in the core. The PTC thermistor components may have a positive temperature coefficient, and the ceramics components may have a thermal conductivity of at least 2.5 W/mK. The ceramics components may be disposed in a distributed manner.

A ceramic dielectric including: a bulk dielectric including barium (Ba) and titanium (Ti); a ceramic nanosheet; and a composite dielectric of the bulk dielectric and the ceramic nanosheet.

In an electronic component including a ceramic body and an external electrode, the external electrode includes a resin layer including a conductive powder and a plating film in direct contact with the resin layer. The plating film includes a metal with a face-centered cubic structure, and a value of F is about 0.20 or more and about 0.50 or less, where F=(P?P.sub.0)/(1?P.sub.0), P.sub.0=I.sub.0(111)/{I.sub.0(111)+I.sub.0(200)+I.sub.0(220)} and P=I(111)/{I(111)+I(200)+I(220)}, and I.sub.0 (111), I.sub.0 (200), and I.sub.0 (220) are diffraction intensities of a (111) plane, a (200) plane, and a (220) plane obtained from known powder X-ray diffraction data for a metal in the plating film, and I (111), I (200), and I (220) are diffraction intensities of a (111) plane, a (200) plane, and a (220) plane obtained from an X-ray diffraction pattern of the plating film.

A chip electronic component includes a ceramic body that includes a semiconductor ceramic including an oxide including Ti and Ba, and a solid metal electrode at an end of the ceramic body and in ohmic contact with the ceramic body. The chip electronic component satisfies: A/V?3.3 (mm.sup.2/mm.sup.3), where A (mm.sup.2) is a surface area of the solid metal electrode, and V (mm.sup.3) is a volume of the ceramic body, and a film stress of the solid metal electrode is about 140 MPa or more.

A positive temperature coefficient ceramic thermistor element includes a sintered thermosensitive ceramic piece that uses lead barium titanate as a base, as well as metal ohmic electrodes which are positioned on two side surfaces of the thermosensitive ceramic piece. The thermistor element has a microporous channel barrier layer, and includes a glass sealing layer which wraps the outer surface of the thermosensitive ceramic piece, or an organic matter sealant which fills and blocks micro-pores in the surfaces of the metal ohmic electrodes combined on the two side surfaces of the thermosensitive ceramic piece and, at the same time, blocks gaps in the surfaces of areas, that do not have the metal ohmic electrodes, of a peripheral edge of the thermosensitive ceramic piece.

A semiconductor ceramic composition including a compound represented by the following general formula (1) as a main component.
(Ba.sub.vBi.sub.xA.sub.yRE.sub.w).sub.m(Ti.sub.uTM.sub.z)O.sub.3(1)
(wherein, A represents both elements of Na and K; RE is at least one element selected from the group consisting of Y, La, Ce, Pr, Nd, Sm, Gd, Dy and Er; and TM is at least one element selected from the group consisting of V, Nb and Ta.)
0.01x0.15(2)
xy0.3(3)
0(w+z)0.01(4)
v+x+y+w=1(5)
u+z=1(6)
0.950m1.050(7)
further, 0.001 mol to 0.055 mol of Ca is included and the ratio of Na/(Na+K) is 0.1 or more and less than 1.

In an embodiment a component includes at least one carrier layer, the carrier layer having a top side and a bottom side and at least one functional layer arranged on the top side of the carrier layer, the functional layer including a material having a specific electrical characteristic, wherein the component is configured for direct integration into an electrical system as a discrete component.