A nonlinear-resistance resin material includes: a plurality of first particles having nonlinear resistance characteristics that exhibit insulation properties when a voltage lower than a threshold value is applied and exhibit conductivity when a voltage equal to or higher than the threshold value is applied; a first resin phase containing second particles that are semiconducting or conducting, and covering at least partially surfaces of some or all of the plurality of first particles; and a second resin phase having insulation properties, and filling voids where none of the first particles and the first resin phase exists. The first particles adjacent to each other are bound and electrically connected to each other via the first resin phase.

A nonlinear-resistance resin material includes: a plurality of first particles having nonlinear resistance characteristics that exhibit insulation properties when a voltage lower than a threshold value is applied and exhibit conductivity when a voltage equal to or higher than the threshold value is applied; a first resin phase containing second particles that are semiconducting or conducting, and covering at least partially surfaces of some or all of the plurality of first particles; and a second resin phase having insulation properties, and filling voids where none of the first particles and the first resin phase exists. The first particles adjacent to each other are bound and electrically connected to each other via the first resin phase.

A surge protection device (SPD) module includes: a housing; a plurality of metal oxide varistor (MOV) wafers, respective ones of the plurality of MOV wafers having electrical characteristics that reduce an imbalance in current between the respective ones of the plurality of MOV wafers in response to an overvoltage event; and one or more electrodes, the plurality of MOV wafers and the one or more electrodes being alternately arranged in the housing.

A surge protection device (SPD) module includes: a housing; a plurality of metal oxide varistor (MOV) wafers, respective ones of the plurality of MOV wafers having electrical characteristics that reduce an imbalance in current between the respective ones of the plurality of MOV wafers in response to an overvoltage event; and one or more electrodes, the plurality of MOV wafers and the one or more electrodes being alternately arranged in the housing.

A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.

A stacked varistor having a small variation in electrostatic capacitance is obtained. The stacked varistor includes first internal electrode projection extending from third internal electrode toward first end surface between first side surface and first varistor region, and second internal electrode projection extending from third internal electrode toward second end surface between first side surface and second varistor region. First internal electrode projection extends closer to first end surface than a line connecting point closest to first end surface of first varistor region and point closest to first end surface of third external electrode is. Second internal electrode projection extends closer to second end surface than a line connecting point closest to second end surface of second varistor region and point closest to second end surface of third external electrode is.

A method for manufacturing a multilayer varistor includes: a first step including providing a multilayer stack in which a plurality of green sheet layers, each containing a Zn oxide powder as a main component and a Pr oxide powder as a sub-component, and a plurality of internal electrode paste layers, each containing a Pd powder, are alternately stacked; and a second step including forming a sintered compact, including an internal electrode inside, by baking the multilayer stack. The second step includes: a first sub-step including baking the multilayer stack by setting an oxygen concentration in an atmosphere at 1000 ppm by volume or less while increasing a temperature from 500 C. to 800 C.; and a second sub-step including baking, after the first sub-step, the multilayer stack by setting the oxygen concentration in the atmosphere at 1000 ppm by volume or more while increasing the temperature to a maximum allowable temperature.

A method for manufacturing a multilayer varistor includes: a first step including providing a multilayer stack in which a plurality of green sheet layers, each containing a Zn oxide powder as a main component and a Pr oxide powder as a sub-component, and a plurality of internal electrode paste layers, each containing a Pd powder, are alternately stacked; and a second step including forming a sintered compact, including an internal electrode inside, by baking the multilayer stack. The second step includes: a first sub-step including baking the multilayer stack by setting an oxygen concentration in an atmosphere at 1000 ppm by volume or less while increasing a temperature from 500 C. to 800 C.; and a second sub-step including baking, after the first sub-step, the multilayer stack by setting the oxygen concentration in the atmosphere at 1000 ppm by volume or more while increasing the temperature to a maximum allowable temperature.

A chip and a method for manufacturing a chip are disclosed. In an embodiment, the chip includes a varistor layer composed of zinc oxide, a multilayered electrode structure which realizes a varistor function in the varistor layer and at least two solderable or bondable external contacts on a first main surface of the varistor layer. The chip further includes a glass layer disposed on the first main surface leaving only the external contacts uncovered, wherein the glass layer includes, as main constituents, oxides of Si and/or Ge, B and K, which in total have at least 70% by weight of the constituents of the glass layer, and wherein the glass layer is substantially free of Al, Ga, Cr and Ti.

A structure and method for fabricating a laterally configured thin film varistor surge protection device using low temperature sputtering techniques which do not damage IC device components contiguous to the varistor being fabricated. The lateral thin film varistor may consist of a continuous layer of alternating regions of a first metal oxide layer and a second metal oxide layer formed between two laterally spaced electrodes using a low temperature sputtering process followed by a low temperature annealing process.