Patent classifications
H01F10/3259
Magnetic structure based on synthetic antiferromagnetic free layer and derivative SOT-MRAM
A magnetic structure includes a magnetic tunnel junction based on a synthetic antiferromagnetic free layer which is regulated by an electric field, and a spin-orbit layer located below the magnetic tunnel junction. The transformation from the antiferromagnetic coupling to the ferromagnetic coupling of the free layer based on a synthetic antiferromagnetic multilayer structure is controlled by an electric field. A spin-orbit torque magnetic random access memory, which includes the magnetic structure, is able to realize stable data writing under the combined interaction of electric field and current, and has advantages of simple structure for scaling, ultralow power consumption, ultrahigh speed of switching, radiation resistance and non-volatility.
Three-dimensional arrays with magnetic tunnel junction devices including an annular discontinued free magnetic layer and a planar reference magnetic layer
A Magnetic Tunnel Junction (MTJ) can include an annular structure and a planar reference magnetic layer disposed about the annular structure. The annular structure can include an annular non-magnetic layer disposed about an annular conductive layer, an annular free magnetic layer disposed about the annular non-magnetic layer, and an annular tunnel insulator disposed about the annular free magnetic layer. The planar reference magnetic layer can be separated from the free magnetic layer by the annular tunnel barrier layer.
Techniques for MRAM top electrode via connection
Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.
MAGNETIC MEMORY DEVICE
According to one embodiment, a magnetic memory device includes a first magnetic region, a first counter magnetic region, and a first nonmagnetic region provided between the first magnetic region and the first counter magnetic region. The first magnetic region includes a first magnetic film, a second magnetic film, and an intermediate film. The first magnetic film is provided between the second magnetic film and the first nonmagnetic region. The intermediate film includes Ru and is provided between the first magnetic film and the second magnetic film. A distance along a first direction between the first magnetic film and the second magnetic film is not less than 1.8 nm and not more than 2.2 nm. The first direction is from the first counter magnetic region toward the first magnetic region.
Magnetoresistive effect element, magnetic head, sensor, high frequency filter, and oscillation element
There is provided a magnetoresistive effect element having improved magnetoresistive effect. A magnetoresistive effect element MR includes a first ferromagnetic layer 4 as a fixed magnetization layer, a second ferromagnetic layer 6 as a free magnetization layer, and a nonmagnetic spacer layer 5 provided between the first ferromagnetic layer 4 and the second ferromagnetic layer 6. The nonmagnetic spacer layer 5 includes at least one of a first insertion layer 5A provided under the nonmagnetic spacer layer 5 and a second insertion layer 5C provided over the nonmagnetic spacer layer 5. The first insertion layer 5A and the second insertion layer 5C are made of Fe.sub.2TiSi.
MAGNETIC RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a magnetic random access memory (MRAM) cell. The MRAM cell includes a first magnetic layer disposed over a substrate, a first non-magnetic material layer made of a non-magnetic material and disposed over the first magnetic layer, a second magnetic layer disposed over the first non-magnetic material layer, and a second non-magnetic material layer disposed over the second magnetic layer. The second magnetic layer includes a plurality of magnetic material pieces separated from each other.
MAGNETIC TUNNEL JUNCTION STRUCTURES AND RELATED METHODS
The disclosure is directed to spin-orbit torque (SOT) magnetoresistive random-access memory (MRAM) (SOT-MRAM) structures and methods. A SOT channel of the SOT-MRAM includes multiple heavy metal layers and one or more dielectric dusting layers each sandwiched between two adjacent heavy metal layers. The dielectric dusting layers each include discrete molecules or discrete molecule clusters of a dielectric material scattered in or adjacent to an interface between two adjacent heavy metal layers.
TECHNIQUES FOR MRAM TOP ELECTRODE VIA CONNECTION
Some embodiments relate to a memory device. The memory device includes a first magnetoresistive random-access memory (MRAM) cell disposed on a substrate, and a second MRAM cell disposed on the substrate. An inter-level dielectric (ILD) layer is disposed over the substrate. The ILD layer comprises sidewalls defining a trough between the first and second MRAM cells. A dielectric layer disposed over the ILD layer. The dielectric layer completely fills the trough.
CRYSTAL SEED LAYER FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM)
Some embodiments relate to a memory device. The memory device includes a magnetoresistive random-access memory (MRAM) cell comprising a magnetic tunnel junction (MTJ). The MTJ device comprises a stack of layers, comprising a bottom electrode disposed over a substrate. A seed layer disposed over the bottom electrode. A buffer layer is disposed between the bottom electrode and the seed layer. The buffer layer prevents diffusion of a diffusive species from the bottom electrode to the seed layer.
TECHNIQUES FOR MRAM MTJ TOP ELECTRODE CONNECTION
Some embodiments relate to a method for manufacturing a memory device. The method includes forming a first masking layer disposed over a dielectric layer, the first masking layer exhibiting sidewalls defining an opening disposed above a magnetoresistive random-access memory (MRAM) cell located in an embedded memory region. A first etch is performed to form a first via opening within the dielectric layer above the MRAM cell. A top electrode via layer formed over the MRAM cell and the dielectric layer. A first planarization process performed on the top electrode via layer to remove part of the top electrode via layer and define a top electrode via having a substantially flat top surface.