Structures of and methods for fabricating fine-scale interconnects and fuses are disclosed. A mushroom-type structure with a narrow stalk supporting a wider cap can be used for fine-scale interconnects with widths on the scale of hundreds of nanometers that have low resistivity. Micro-air bridges can be introduced by omitting the stalk in sections of the interconnect, allowing the interconnect to bridge over obstacles. The mushroom-type micro-air bridge structure can also be modified to create fine-scale fuses that have low resistivity overall and sections of significantly higher resistivity where the micro-air bridges exist. The significantly higher resistivity results in preferential fusing at the micro-air bridges. Both mushroom interconnects and mushroom fuses can be fabricated using electron beam lithography.

An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I<ITIF, where the breaking current IT of the fuse is a minimum current that causes the fuse to open.

The present application discloses a circuit board and a method for manufacturing the same, and a terminal test device. The circuit board includes a base substrate, and a plurality of conductive lines on the base substrate, each of the plurality of conductive lines having one end configured to be connected with a signal output bus of a signal generator and the other end configured to be connected with a terminal. A fuse is connected in series in each conductive line, and a breaking current IT of the fuse, a maximum operating current I of the conductive line and a fault current IF of the conductive line satisfy: I<ITIF, where the breaking current IT of the fuse is a minimum current that causes the fuse to open.

To produce a cost-effective fuse in chip design, which is applied to a carrier substrate made of a Al.sub.2O.sub.3 ceramic having a high thermal conductivity, and which is provided with a fusible metallic conductor and a cover layer, in which the melting point of the metallic conductor may be defined reliably, it is suggested that an intermediate layer having low thermal conductivity be positioned between the carrier substrate and the metallic conductor, the intermediate layer being formed by a low-melting-point inorganic glass paste applied in the screen-printing method or an organic intermediate layer applied in island printing. Furthermore, a method for manufacturing the fuse is specified.

To produce a cost-effective fuse in chip design, which is applied to a carrier substrate made of a Al.sub.2O.sub.3 ceramic having a high thermal conductivity, and which is provided with a fusible metallic conductor and a cover layer, in which the melting point of the metallic conductor may be defined reliably, it is suggested that an intermediate layer having low thermal conductivity be positioned between the carrier substrate and the metallic conductor, the intermediate layer being formed by a low-melting-point inorganic glass paste applied in the screen-printing method or an organic intermediate layer applied in island printing. Furthermore, a method for manufacturing the fuse is specified.

Devices and systems are provided that incorporate fusible links within the electrical traces of a battery module voltage sensing circuit. The fusible links can be integrally formed in an electric trace and provide an overcurrent protection feature for the circuit without requiring fuse elements or components that are separate from the electrical trace. Each of these fusible links include a substantially flat controlled cross-sectional area disposed along a length of the material making up the electrical trace. In an overcurrent situation, the connection between a battery management system and a battery cell may be severed by the overcurrent melting the fusible link. The electrical traces may be spaced apart from one another in the circuit such that an overcurrent situation breaking the connection between one cell and the battery management system would not affect adjacent electrical traces not having an overcurrent situation.

A printed fuse fabrication is provided. The printed fuse includes a low thermal conductivity ceramic substrate and a fusible element printed on the substrate. The fusible element printed on the substrate includes a series of portions of reduced printed thickness, defining weak spots for fusible operation of the fusible element, respectively separated by portions of increased printed thickness.

A printed fuse fabrication is provided. The printed fuse includes a low thermal conductivity ceramic substrate and a fusible element printed on the substrate. The fusible element printed on the substrate includes a series of portions of reduced printed thickness, defining weak spots for fusible operation of the fusible element, respectively separated by portions of increased printed thickness.