A consumable part for a plasma processing chamber includes a plasma facing side. An engineered surface is formed into the plasma facing side of the consumable part. A plurality of raised features defines the engineered surface, wherein features are arranged in a predefined pattern, wherein each of the plurality of raised features includes a top region having an outer edge and a sidewall. A base surface of the engineered surface is configured to surround each of the plurality of raised features, such that a corresponding sidewall of a corresponding raised feature extends up at an angle from the base surface to a corresponding top region. The consumable part is configured to be installed in the plasma processing chamber. The consumable part is configured to be exposed to a plasma and byproducts of the plasma.

A method of making a semiconductor manufacturing apparatus member includes a step of preparing an aluminum base having an alumite layer having a porous columnar structure at an upper surface thereof. The alumite layer is an anodic oxidation film, and a Young's modulus of the alumite layer is between 90 GPa and 120 GPa. The method also includes a step of forming a particle-resistant layer on the alumite layer by aerosol deposition, in which an aerosol containing fine particles of a brittle material dispersed in a gas is ejected from a nozzle to impact against a surface of the alumite layer, wherein the particle-resistant layer includes a polycrystalline ceramic; and wherein, when the resulting semiconductor manufacturing apparatus member is exposed to a plasma in a reference plasma resistance test, the particle-resistant layer has an arithmetic average height Sa of 0.060 or less after the reference plasma test is completed.

A plasma chamber includes a chamber body having a processing region therewithin, a liner disposed on the chamber body, the liner surrounding the processing region, a substrate support disposed within the liner, a magnet assembly comprising a plurality of magnets disposed around the liner, and a magnetic-material shield disposed around the liner, the magnetic-material shield encapsulating the processing region near the substrate support.

Provided is a vacuum processing apparatus which is capable of performing baking processing of a deposition preventive plate without impairing the function of being capable of cooling the deposition preventive plate disposed inside a vacuum chamber. The vacuum processing apparatus has a vacuum chamber for performing a predetermined vacuum processing on a to-be-processed substrate that is set in position inside the vacuum chamber. A deposition preventive plate is disposed inside the vacuum chamber. Further disposed are: a metallic-made block body vertically disposed on an inner surface of the lower wall of the vacuum chamber so as to lie opposite to a part of the deposition preventive plate with a clearance thereto; a cooling means for cooling the block body; and a heating means disposed between the part of the deposition preventive plate and the block body to heat the deposition preventive plate by heat radiation.

The present invention provides a method for plasma dicing a substrate. The substrate is placed onto a support film on a frame to form a work piece. A die attach film is adhered to the substrate. A process chamber having a plasma source is provided. The work piece is placed into the process chamber. A plasma is generated from the plasma source in the plasma process chamber. The work piece is processed using the generated plasma and a byproduct generated from the die attach film while the die attach film is exposed to the generated plasma.

Techniques for depositing a functionally integrated coating structure on a substrate are provided. An example method according to the disclosure includes receiving the substrate into a process chamber of a multi-process ion beam assisted deposition system, disposing the substrate in a first zone including a first evaporator species and a first ion beam, wherein the first evaporator species is Aluminum Oxide (Al2O3), disposing the substrate in a second zone including a second evaporator species and a second ion beam, wherein the second evaporator species is Yttrium Oxide (Y2O3), and disposing the substrate in a third zone including a third evaporator species and a third ion beam, wherein the third evaporator species is Yttrium Fluoride (YF3).

Exemplary semiconductor processing chambers may include a chamber body. The chambers may include a showerhead. The chambers may include a substrate support. The substrate support may include a platen characterized by a first surface facing the showerhead. The substrate support may include a shaft coupled with the platen along a second surface of the platen opposite the first surface of the platen. The shaft may extend at least partially through the chamber body. A coating may extend conformally about the first surface of the platen, the second surface of the platen, and about the shaft.

Disclosed are embodiments for an engineered feature formed as a part of or on a chamber component. In one embodiment, a chamber component for a processing chamber includes a component part body having unitary monolithic construction. The component part body has an outer surface. An engineered complex surface is formed on the outer surface. The engineered complex surface has a first lattice framework formed from a plurality of first interconnected laths and a plurality of first openings are bounded by three or more laths of the plurality of laths.

Embodiments described herein generally relate to a method and apparatus for fabricating a chamber component for a plasma process chamber. In one embodiment a chamber component used within a plasma processing chamber is provided that includes a metallic base material comprising a roughened non-planar first surface, wherein the roughened non-planar surface has an Ra surface roughness of between 4 micro-inches and 80 micro-inches, a planar silica coating formed over the roughened non-planar surface, wherein the planar silica coating has a surface that has an Ra surface roughness that is less than the Ra surface roughness of the roughened non-planar surface, a thickness between about 0.2 microns and about 10 microns, less than 1% porosity by volume, and contains less than 2E.sup.12 atoms/centimeters.sup.2 of aluminum.

Exemplary deposition methods may include forming a plasma of an oxygen-containing precursor within a processing region of a semiconductor processing chamber. The processing region may house a semiconductor substrate on a substrate support. The methods may include, while maintaining the plasma of the oxygen-containing precursor, flowing a silicon-containing precursor through a faceplate into the processing region of the semiconductor processing chamber. The faceplate may have an impedance of at least 5.75 deciohm. The methods may include depositing a silicon-containing material on the semiconductor substrate.