A bonding wafer structure includes a support substrate, a bonding layer, and a silicon carbide (SiC) layer. The bonding layer is formed on a surface of the support substrate, and the SiC layer is bonded onto the bonding layer, in which a carbon surface of the SiC layer is in direct contact with the bonding layer. The SiC layer has a basal plane dislocation (BPD) of 1,000 ea/cm.sup.2 to 20,000 ea/cm.sup.2, a total thickness variation (TTV) greater than that of the support substrate, and a diameter equal to or less than that of the support substrate. The bonding wafer structure has a TTV of less than 10 μm, a bow of less than 30 μm, and a warp of less than 60 μm.

An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes connecting a drum which stores the chemical liquid with a testing pipe. The method also includes guiding the chemical liquid in the drum into the testing pipe. In addition, the method includes detecting a condition of the chemical liquid in the testing pipe. The method further includes determining if the condition of the chemical liquid is acceptable. When the condition of the chemical liquid is acceptable, supplying the chemical liquid to a processing tool at which the semiconductor wafer is processed.

Various embodiments provide an apparatus and method for fabricating a wafer, such as a SiC wafer. The apparatus includes a support having a plurality of arms for supporting a substrate. The arms allows for physical contact between the support and the substrate to be minimized. As a result, when the substrate is melted, surface tension between the arms and molten material is reduced, and the molten material will be less likely to cling to the support.

A substrate processing apparatus includes a pair of first substrate chucks each configured to hold a substrate from below while allowing a first main surface of the substrate to face upwards; a pair of second substrate chucks each configured to hold the substrate from below while allowing a second main surface of the substrate opposite to the first main surface to face upwards; a rotary table which is configured to be rotated about a rotation axis; a first processing unit equipped with a first processing tool configured to process the first main surface of the substrate held by the first substrate chuck; and a second processing unit equipped with a second processing tool configured to process the second main surface of the substrate held by the second substrate chuck.

Various embodiments provide an apparatus and method for fabricating a wafer, such as a SiC wafer. The apparatus includes a support having a plurality of arms for supporting a substrate. The arms allows for physical contact between the support and the substrate to be minimized. As a result, when the substrate is melted, surface tension between the arms and molten material is reduced, and the molten material will be less likely to cling to the support.

Disclosed are an epitaxial wafer and a method of fabricating the same, and an electrochemical sensor, wherein the reference electrode comprises: a substrate (11); an InGaN layer (12) formed on a surface of the substrate (11) and having an In content between 20% and 60% so as to ensure that a transition from negatively charged surface states to positively charged surface states occurs within a composition range; and an InN layer (13) formed on a surface of the InGaN layer (12) facing away from the substrate (11) to act as a stabilization layer. The InGaN layer (12) with an In content between 20% and 60% allows generation of an electrochemical response independent of the concentration of a solution to be detected; and in addition, the InN layer (13) with a high density of intrinsic, positively charged surface states further improves the electrochemical stability of the reference electrode.

Provided is an epitaxial growth apparatus which makes it possible to prevent the production of debris between a preheat ring and a lower liner without fracturing the preheat ring. The epitaxial growth apparatus includes: a chamber; an upper liner and a lower liner that are disposed on an inner wall of the chamber; a susceptor being provided inside the chamber; and a preheat ring that is disposed on a supporting portion protruding in an opening of the lower liner and is disposed on the outer circumference of the susceptor. The preheat ring is not supported by the supporting portion in at least a part of a region that is right above a region where the semiconductor wafer passes in a transfer path in which the semiconductor wafer is loaded into the chamber to be set on the susceptor.

A method of manufacturing a semiconductor structure includes the following steps: providing a first semiconductor wafer, wherein the first semiconductor wafer includes a first dielectric layer and at least one first top metallization structure embedded in the first dielectric layer, and a top surface of the first dielectric layer is higher than a top surface of the first top metallization structure by a first distance; providing a second semiconductor wafer, wherein the second semiconductor wafer includes a second dielectric layer and at least one second top metallization structure embedded in the second dielectric layer, and a top surface of the second top metallization structure is higher than a top surface second dielectric layer of the by a second distance; and hybrid-bonding the first semiconductor wafer and the second semiconductor wafer.