Semiconductor wafers, are processed using minimally three processing operations: a first double-sided polishing operation, a second chemical-mechanical polishing operation and an epitaxial coating operation. A control system for conducting the method defines at least one operating parameter for the processing operations specifically based on at least one wafer parameter measured on the semiconductor wafer after processing in at least one processing operation, based on an actual state of a processing apparatus with which the respective processing operation is conducted, and based on optimizing wafer parameters for flatness after the wafer has undergone all three processing operations instead of optimizing each individual processing step for optimal flatness.

An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.

A method for manufacturing a gallium nitride semiconductor device includes: preparing a gallium nitride wafer; forming an epitaxial growth film on the gallium nitride wafer to provide a processed wafer having chip formation regions; perform a surface side process on a one surface side of the processed wafer; removing the gallium nitride wafer and dividing the processed wafer into a chip formation wafer and a recycle wafer; and forming an other surface side element component on an other surface side of the chip formation wafer.

A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

A method includes etching a first oxide layer in a wafer. The etching is performed in an etcher having a top plate overlapping the wafer, and the top plate is formed of a non-oxygen-containing material. The method further includes etching a nitride layer underlying the first oxide layer in the etcher until a top surface of a second oxide layer underlying the nitride layer is exposed. The wafer is then removed from the etcher, with the top surface of the second oxide layer exposed when the wafer is removed.

A bonded wafer includes: a first wafer having a first surface and a second surface opposite to the first surface, and including a functional element on the first surface; and a second wafer in which a structure having at least one of a hole, a groove and a cavity is formed; wherein an annular protrusion is formed to have a shape to extend along an outer periphery on the second surface of the first wafer; wherein at least a portion of the second wafer is a reduced-diameter portion having a diameter smaller than an inner diameter of the annular protrusion; and wherein, under a state in which the reduced-diameter portion is fitted into a region surrounded by the annular protrusion of the first wafer, the second wafer is bonded to the second surface at least at the region.

There is provided a method of manufacturing a device, which comprises: a preparation step of preparing a workpiece having a recess formed therein; a burying step of burying a sacrificial material composed of a thermally decomposable organic material in the recess; a lamination step of laminating a preliminary sealing film on the sacrificial material buried in the recess; a first removal step of removing the sacrificial material in the recess through the preliminary sealing film, by annealing the workpiece at a first temperature and thermally decomposing the sacrificial material; a processing step of performing a predetermined process on a portion other than the recess in the workpiece, in a state in which the recess is covered with the preliminary sealing film; and a second removal step of removing the preliminary sealing film.

In accordance with some embodiments, a method for processing semiconductor wafer is provided. The method includes connecting a drum which stores the chemical liquid with a testing pipe. The method also includes guiding the chemical liquid in the drum into the testing pipe. In addition, the method includes detecting a condition of the chemical liquid in the testing pipe. The method further includes determining if the condition of the chemical liquid is acceptable. When the condition of the chemical liquid is acceptable, supplying the chemical liquid to a processing tool at which the semiconductor wafer is processed.

A method of forming a memory device includes: forming a polish stop layer over a metallization layer in an inter-metal dielectric layer; performing an etching process to form an opening in the polish stop layer, in which a sidewall of the opening extends at an acute angle relative to a top surface of the polish stop layer; forming an electrode material in the opening and over the polish stop layer; planarizing the electrode material until a top surface of the polish stop layer is exposed so as to form a bottom electrode surrounded by the polish stop layer; and forming a stack of a resistance switching layer and a top electrode over the bottom electrode.

A memory device includes a metal structure, a first dielectric layer, a bottom electrode, a second dielectric layer, a resistance switching layer, and a top electrode. The first dielectric layer surrounds the metal structure. The bottom electrode is in contact with a top surface of the metal structure. The second dielectric layer surrounds the bottom electrode, in which a top surface of the bottom electrode is higher than a top surface of the second dielectric layer. The resistance switching layer is over the bottom electrode. The top electrode is over the resistance switching layer.