The polishing pad is suitable for polishing or planarizing a wafer of at least one of semiconductor, optical and magnetic substrates. The polishing pad includes radial feeder grooves in a polishing layer separating the polishing layer into polishing regions. The radial feeder grooves extend at least from a location adjacent the center to a location adjacent the outer edge of the polishing pad. Each polishing region including a series of biased grooves that connects a pair of adjacent radial feeder grooves. A majority of the biased grooves having either an inward bias toward the center of the polishing pad or an outward bias for directing polishing fluid toward the outer edge of the polishing pad.

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Direct growth methods for preparing diamond-assisted heat-dissipation silicon carbide substrates of GaN-HEMTs are disclosed. In an embodiment, the direct growth method includes the following steps: (1) etching holes in a surface of a silicon carbide substrate to produce a silicon carbide wafer; (2) ultrasonic cleaning the produced silicon carbide wafer; (3) establishing an auxiliary nucleation point on a surface of the silicon carbide wafer; (4) depositing a diamond layer; (5) removing the portion of the diamond layer on the upper surface while retaining the portion of the diamond layer in the holes; (6) ultrasonic cleaning; and (7) depositing diamond in the holes on the silicon carbide wafer until the holes are fully filled.

A method includes: in a semiconductor wafer including a first semiconductor layer and a second semiconductor layer adjoining the first semiconductor layer, forming a porous region extending from a first surface into the first semiconductor layer; and removing the porous region by an etching process, wherein a doping concentration of the second semiconductor layer is less than 10.sup.2 times a doping concentration of the first semiconductor layer and/or a doping type of the second semiconductor layer is complementary to a doping type of the first semiconductor layer.

The disclosure herein includes compositions and methods for ionizing targets and methods for making the compositions. In some embodiments, the compositions can include a porous substrate that has been etched for a desired average pore size, a desired porosity, or both for detection of one or more targets of interest. Also disclosed herein are methods for using the composition to ionize targets.

Provided are display device and method for fabricating the same. According to an aspect of the present disclosure, there is provided a display device comprising: a first substrate; at least one wavelength conversion layer disposed on the first substrate; a capping layer disposed on the wavelength conversion layer and comprising a porous layer; and a first polarizing layer disposed on the capping layer.

A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

Disclosed is a semiconductor processing apparatus including one or more components having a conductive or nonconductive porous material. In some embodiments, an ion implanter may include a plurality of beam line components for directing an ion beam to a target, and a porous material along a surface of at least one of the plurality of beamline components.

The invention provides a method for polishing or planarizing a wafer of at least one of semiconductor, optical and magnetic substrates. The method includes rotating a polishing pad having radial feeder grooves in a polishing layer separating the polishing layer into polishing regions. The radial feeder grooves extend at least from a location adjacent the center to a location adjacent the outer edge. Each polishing region includes a series of biased grooves connecting a pair of adjacent radial feeder grooves. The series of biased grooves separate a land area and have inner walls closer to the center and outer walls closer to the outer edge. Pressing and rotating the wafer against the rotating polishing pad for multiple rotations polishes or planarizes the wafer with land areas wet by the overflowing polishing fluid.

A semiconductor system includes a silicon substrate and a porous silicon region disposed on the silicon substrate. The porous silicon region is configured to passivate the surface of the silicon substrate via a field effect and to reduce reflection loss on the silicon substrate via an appropriate refractive index. The porous silicon region is manufactured by a stain etching process, which retrofits existing tools for junction isolation and Phosphorus Silicon Glass (PSG) etch in solar cell manufacturing. The retrofitted tools for junction isolation and PSG etch achieves multiple purposes in a single step, including etch-back, PSG etch, antireflection coating, and passivation of the front surface of the solar cell.