A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer can be made of an insulating material or metal. A trench is formed in the surface of the base material. The covering layer extends into the trench to provide the cantilevered protrusion of the covering layer. A portion of the base material is removed by plasma etching to form a cantilevered protrusion extending beyond an edge of the base material. The cantilevered protrusion can be formed by removing the base material to the covering layer, or the cantilevered protrusion can be formed within the base material under the covering layer. A second semiconductor die is disposed partially under the cantilevered protrusion. An interconnect structure is formed between the cantilevered protrusion and second semiconductor die.

A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.

Implementations of a packaging system may include a wafer; and a curvature adjustment structure coupled thereto where the curvature adjustment structure may be configured to alter a curvature of a largest planar surface of the wafer.

A method of manufacturing an integrated circuit may include placing cells, based on input data defining the integrated circuit, performing a pin reordering operation on a plurality of pins in a first cell of the cells, based on physical information regarding the pins in the first cell, wherein the physical information is determined based on the placement of the cells, performing a routing operation on the cells after the pin reordering operation, and manufacturing the integrated circuit, based on a layout produced by the routing operation.

The present disclosure provides a method for wafer bonding, including providing a wafer, forming a sacrificial layer on a top surface of the first wafer, trimming an edge of the first wafer to obtain a first wafer area, cleaning the top surface of the first wafer, removing the sacrificial layer, and bonding the top surface of the first wafer to a second wafer having a second wafer area greater than the first wafer area.

High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

A method of producing a GaAs wafer having excellent OF orientation stability even in a GaAs wafer having an off angle, and a GaAs wafer group are provided. A method of producing a GaAs wafer includes: a grinding step of grinding a peripheral surface of a GaAs ingot including formation of a provisional orientation flat; a slicing step of slicing the GaAs ingot after the grinding step to cut out a material wafer having an off angle; and a cleaving step of applying marking to the material wafer according to an orientation of an orientation flat determined based on the provisional orientation flat and cleaving the material wafer toward a peripheral surface of the material wafer from the marking to form the orientation flat.

A semiconductor wafer according to an embodiment includes a support region facing a support member, an outer circumferential region positioned on an outer side of the support region, and an inner circumferential region positioned on an inner side of the support region. The outer circumferential region has a convex portion with a thickness protruded upward with respect to the inner circumferential region or a concave portion with a thickness recessed downward with respect to the inner circumferential region.

A silicon carbide epitaxial substrate includes a silicon carbide substrate, a first silicon carbide epitaxial layer, and a second silicon carbide epitaxial layer. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The first silicon carbide epitaxial layer is in contact with a whole of the first main surface. The second silicon carbide epitaxial layer is in contact with a whole of the second main surface. A carrier concentration of the silicon carbide substrate is higher than a carrier concentration of each of the first silicon carbide epitaxial layer and the second silicon carbide epitaxial layer.

A substrate for epitaxial growth includes a central region that has a center of the substrate and that serves as a non-modified region, and a peripheral region that surrounds the central region in a manner to be spaced apart from the center of the substrate by a distance and that serves as a modified region having a plurality of modified points. A method for manufacturing a substrate for epitaxial growth includes providing a substrate and forming a plurality of modified points in an interior of the substrate in position corresponding to the modified region. A semiconductor device including the substrate and a method for manufacturing the semiconductor device are also disclosed.