Patent classifications
H01L21/02068
Fin field-effect transistor device and method of forming the same
In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.
FILM FORMING METHOD AND FILM FORMING APPARATUS
A film forming method includes preparing a substrate having a first region in which a metal film or an oxide film of the metal film is exposed, and a second region in which an insulating film is exposed, supplying, to the substrate, an organic compound containing, in a head group, a triple bond between carbon atoms represented by Chemical Formula (1) described in the specification, causing the organic compound to be selectively adsorbed in the first region among the first region and the second region, and cleaving the triple bond in the first region and forming a hydrophobic film having a honeycomb structure of carbon atoms through polymerization.
Substrate processing method and substrate processing apparatus
The substrate processing method includes a hydrophilization step of hydrophilizing a surface of a substrate, a processing liquid supplying step of supplying a processing liquid to the hydrophilized surface of the substrate, a processing film forming step in which the processing liquid supplied to the surface of the substrate is solidified or cured to form a processing film on the surface of the substrate, and a peeling step in which a peeling liquid is supplied to the surface of the substrate to peel the processing film from the surface of the substrate. The peeling step includes a penetrating hole forming step in which the processing film is partially dissolved in the peeling liquid to form a penetrating hole in the processing film.
Methods for depositing blocking layers on conductive surfaces
Methods of selectively depositing blocking layers on conductive surfaces over dielectric surfaces are described. In some embodiments, a carboxylic acid is exposed to a substrate to selectively form a blocking layer. In some embodiments, a hydrazide is exposed to a substrate to selectively form a blocking layer. In some embodiments, an alkyl phosphonic acid is exposed to a substrate to selectively form a blocking layer. In some embodiments, the alkyl phosphonic acid is formed in-situ and exposed to the substrate. In some embodiments, a layer is selectively deposited on the dielectric surface after the blocking layer is formed.
ATOMIC LAYER ETCHING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME
An atomic layer etching method capable of precisely etching a metal thin film at units of atomic layer from a substrate including the metal thin film, includes forming a metal layer on a substrate, and etching at least a portion of the metal layer. The etching at least a portion of the metal layer includes at least one etching cycle. The at least one etching cycle includes supplying an active gas onto the metal layer, and supplying an etching support gas after supplying the active gas. The etching support gas is expressed by the following general formula
##STR00001##
wherein each of R1, R2, R3, R4 and R5 independently includes hydrogen or a C.sub.1-C.sub.4 alkyl group, and N is nitrogen.
Selective internal gate structure for ferroelectric semiconductor devices
The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.
Method of metal gate formation and structures formed by the same
A method includes: providing a substrate; forming a first pair of source/drain regions in the substrate; disposing an interlayer dielectric layer over the substrate, the interlayer dielectric layer having a first trench between the first pair of source/drain regions; depositing a dielectric layer in the first trench; depositing a barrier layer over the dielectric layer; performing an operation on the substrate; removing the barrier layer from the first trench to expose the dielectric layer subsequent to the operation; and depositing a work function layer over the dielectric layer in the first trench.
METHOD FOR RESOLVING DEFECT OF SURFACE STRUCTURE OF TRENCH AND METHOD FOR PREPARING SEMICONDUCTOR STRUCTURE
The embodiments of the present disclosure propose a method for resolving a defect of surface structures of trenches and a method for preparing a semiconductor structure. The method for resolving a defect of surface structures of trenches includes: cleaning the trenches on a base with a cleaning liquid after the trenches are formed on the base, where the cleaning liquid is water.
PREPARATION METHOD OF METAL CONNECTING LINE
A preparation method of a metal connecting line includes: providing a base, where the base includes a metal conductive structure; patterned etching the base to expose a surface of the metal conductive structure; treating a surface of the base by oxygen-containing plasma to remove a charge on the surface of the metal conductive structure; and cleaning the surface of the metal conductive structure by hydrogen.
CLEANING MACHINE AND CLEANING METHOD
Disclosed in the present disclosure are a cleaning machine and a cleaning method. The cleaning machine includes: a wet cleaning module, configured to execute a wet cleaning process on a wafer; a dry cleaning module, configured to execute a dry cleaning process on the wafer; a conveying module, configured to input the wafer into the wet cleaning module or the dry cleaning module, or output the wafer from the wet cleaning module or the dry cleaning module; a transferring module, configured to transfer the wafer from the wet cleaning module to the dry cleaning module or transfer the wafer from the dry cleaning module to the wet cleaning module; and a processing module, configured to extract gas from the transferring module.