Described herein is a technique capable of improving the uniformity of device characteristics. A method of manufacturing a semiconductor device may include: (a) accommodating in a process chamber a substrate having an organic film thereon; (b) supplying a metal-containing gas to the substrate; (c) supplying a first oxygen-containing gas and a dilute gas to the substrate, the dilute gas containing at least one of a second oxygen-containing gas and an inert gas; (d) performing a cycle a predetermined number of time, the cycle including (b) and (c), wherein a flow rate of the first oxygen-containing gas is equal to or greater than a flow rate of the dilute gas in one of the cycle performed the predetermined number of time.

A process for fabricating an integrated circuit is provided. The process includes providing a substrate, forming a hard mask upon the substrate by one of atomic-layer deposition and molecular-layer deposition, and exposing the hard mask to a charged particle from one or more charged particle beams to pattern a gap in the hard mask. In the alternative, the process includes exposing the hard mask to a charged particle from one or more charged-particle beams to pattern a structure on the hard mask.

There is provided a method of forming an insulating film which includes providing a workpiece having a base portion and a protuberance portion formed to protrude from the base portion; and forming an insulating film on the workpiece by sputtering. The forming an insulating film includes forming the insulating film while changing an angle defined between the workpiece and a target.

A structure is provided that comprises a substrate, a plurality of elements, and a plurality of trenches disposed on the substrate. Each element is separated from adjacent elements by a trench in the plurality of trenches and has a top surface with a first and an opposing second side. A first portion of the top surface is on the first side and a second portion of the top surface is on the opposing second side. The structure further comprises a plurality of first graphene layers, each of which is formed on the first portion of the top surface of an element in the plurality of elements. The structure further comprises a plurality of second graphene layers, each of which is formed on the second portion of the top surface of a corresponding element so that each element is separately overlayed by a first graphene layer and a second graphene layer.

The disclosure provides a liquid crystal display panel, an array substrate and a manufacturing method thereof. In the method, controllable resistance spacer layers are formed on at least one of a source doped region and a drain doped region of a low temperature polysilicon active layer, wherein when a turn-on signal is not applied to the gate layer, the controllable resistance spacer layers serve as a blocking action for a flowing current, and when the turn-on signal is applied to the gate layer, the controllable resistance spacer layers serve as a conducting action for the flowing current, such that a contact region formed of the controllable resistance spacer layers is connected the corresponding source layer and the corresponding drain through the controllable resistance spacer layers. Therefore, the disclosure is capable of effectively decreasing a leakage of a thin film transistor.

A method of forming a graphite-based structure on a substrate comprises patterning the substrate thereby forming a plurality of elements on the substrate. Each respective element in the plurality of elements is separated from an adjacent element on the substrate by a corresponding trench in a plurality of trenches on the substrate and each respective element in the plurality of elements has a corresponding top surface. The method further comprises segmentedly depositing a graphene initiating layer onto the top surface of each respective element in the plurality of elements; and generating graphene using the graphene initiating layer thereby forming the graphite-based structure.

A passivation method for a silicon carbide (SiC) surface may include steps of providing a silicon carbide surface, depositing a thin metal layer on the silicon carbide surface, forming a first passivation layer on the metal layer at low temperature, and generating a dielectric layer by a reaction between a gas/liquid ambient and the thin metal layer. In one embodiment, the thin metal layer is deposited on the silicon carbide surface by sputtering, e-beam evaporation, electroplating, etc. In another embodiment, the metal may include, but not limited to, aluminum, magnesium, etc. In a further embodiment, the passivation layer can be a low temperature oxide and/or nitride layer. In still a further embodiment, the dielectric layer can be aluminum oxide, titanium di-oxide etc. The passivation method for a silicon carbide (SiC) may further include a step of forming a second passivation layer on the first passivation layer.

A method of manufacturing a semiconductor device includes processing a substrate accommodated in a process container accommodated in a housing by supplying a process gas onto the substrate; and exhausting the process container using an exhaust system comprising a first exhaust pipe connected to the process container, the first exhaust pipe having circular or oval cross-section perpendicular to an exhausting direction thereof; and a second exhaust pipe connected to the first exhaust pipe, the second exhaust pipe having square or rectangular cross-section perpendicular to the exhausting direction, wherein at least a portion of the second exhaust pipe is disposed within the housing.

A method includes providing a substrate having a first conductive feature in a first dielectric material layer; forming a first etch stop layer on the first dielectric material layer, wherein the first etch stop layer is formed of a high-k dielectric material; forming a second etch stop layer on the first etch stop layer; forming a second dielectric material layer on the second etch stop layer; forming a pattered mask layer on the second dielectric material layer; forming a first trench in the second dielectric material layer and the second etch stop layer; removing a portion of the first etch stop layer through the first trench to thereby form a second trench, wherein removing the portion of the first etch stop layer includes applying a solution to the portion of the first etch stop layer; and forming a second conductive feature in the second trench.

Methods for removing a passivation film from a copper surface can include exposing the passivation film to a vapor phase organic reactant, for example at a temperature of 100 C. to 400 C. In some embodiments, the passivation film may have been formed by exposure of the copper surface to benzotriazole, such as can occur during a chemical mechanical planarization process. The methods can be performed as part of a process for integrated circuit fabrication. A second material can be selectively deposited on the cleaned copper surface relative to another surface of the substrate.