A method of fabricating a device including a two-dimensional (2D) material includes forming an amorphous transition metal oxide structure on a substrate and replacing the amorphous transition metal oxide structure by a transition metal dichalcogenide structure. The transition metal dichalcogenide structure includes atomic layers, that are substantially parallel to a surface of the transition metal dichalcogenide structure.

A method of fabricating a device including a two-dimensional (2D) material includes forming a transition metal oxide pattern on a substrate and forming a transition metal dichalcogenide layer on a top surface and a side surface of a residual portion of the transition metal oxide pattern. The forming the transition metal dichalcogenide layer may include replacing a surface portion of the transition metal oxide pattern with the transition metal dichalcogenide layer. The transition metal dichalcogenide layer includes at least one atomic layer that is substantially parallel to a surface of the residual portion of the transition metal oxide pattern.

Disclosed is a method for obtaining a field effect transistor, including steps of: forming a multi-layer graphene stack on a face of a base substrate; depositing a source and a drain electrode on the multi-layer graphene stack; forming a conductive multi-layer graphene block by lithography and etching process; fluorinating the graphene block, using the source and d rain electrodes as a fluorination-protective mask, during a predetermined period and at a predetermined temperature, such that an upper part of the graphene block is converted into fluorographene over a given thickness portion, to form a dielectric element with in the graphene block; depositing a gate electrode on the dielectric element.

A protective film forming method is provided. In the method, an oxide film of either an organic metal compound or an organic metalloid compound is deposited on a flat surface region between adjacent recessed shapes formed in a surface of a substrate. Then, a lateral portion of the oxide film deposited on the flat surface region is removed by etching.

A method of forming a semiconductor structure includes forming a silicon-germanium layer on a semiconductor region of a substrate having a specific concentration of germanium atoms. The semiconductor region and the silicon-germanium layer are annealed to induce a non-homogenous thermal diffusion of germanium atoms from the silicon-germanium layer into the semiconductor region to form a graded silicon-germanium region. Another method of forming a semiconductor structure includes etching a semiconductor region of the substrate to form a thinned semiconductor region. A silicon-germanium layer is formed on the thinned semiconductor region having a graded germanium concentration profile.

A method for manufacturing a semiconductor device includes: providing a carrier wafer and a silicon carbide wafer; bonding a first side of the silicon carbide wafer to the carrier wafer; splitting the silicon carbide wafer bonded to the carrier wafer into a silicon carbide layer thinner than the silicon carbide wafer and a residual silicon carbide wafer, the silicon carbide layer remaining bonded to the carrier wafer during the splitting; and forming a graphene material on the silicon carbide layer.

Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500 C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500 C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

A substrate includes: a support substrate having a first main surface and a surface layer region which includes at least the first main surface and is formed of any one material selected from the group consisting of boron nitride, molybdenum disulfide, tungsten disulfide, niobium disulfide, and aluminum nitride; and a graphene film disposed on the first main surface and having an atomic arrangement oriented in relation to an atomic arrangement of the material forming the surface layer region. Accordingly, the substrate is provided that enables a high mobility to be stably ensured in an electronic device manufactured to include the graphene film forming an electrically conductive portion.

A silicon carbide-graphite composite is described, including (i) interior bulk graphite material and (ii) exterior silicon carbide matrix material, wherein the interior bulk graphite material and exterior silicon carbide matrix material inter-penetrate one another at an interfacial region therebetween, and wherein graphite is present in inclusions in the exterior silicon carbide matrix material. Such material may be formed by contacting a precursor graphite article with silicon monoxide (SiO) gas under chemical reaction conditions that are effective to convert an exterior portion of the precursor graphite article to a silicon carbide matrix material in which graphite is present in inclusions therein, and wherein the silicon carbide matrix material and interior bulk graphite material interpenetrate one another at an interfacial region therebetween. Such silicon carbide-graphite composite is usefully employed in applications such as implant hard masks in manufacturing solar cells or other optical, optoelectronic, photonic, semiconductor and microelectronic products, as well as in ion implantation system materials, components, and assemblies, such as beam line assemblies, beam steering lenses, ionization chamber liners, beam stops, and ion source chambers.

Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500 C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500 C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.