A FinFET device includes a fin formed in a semiconductor substrate, a gate structure positioned above a portion of the fin, and source and drain regions positioned on opposite sides of the gate structure, wherein the semiconductor substrate includes a first semiconductor material. A silicon-carbide (SiC) semiconductor material is positioned above the fin in the source region and the drain region, wherein the silicon-carbide (SiC) semiconductor material is different from the first semiconductor material. A graphene contact is positioned on and in direct physical contact with the silicon-carbide (SiC) semiconductor material in each of the source region and the drain region, and first and second contact structures are conductively coupled to the graphene contacts in the source region and the drain region, respectively.

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.

A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.

In accordance with an example embodiment of the present invention, a device comprising one or more porous graphene layers, the or each graphene porous layer comprising a multiplicity of pores. The device may form at least part of a flexible and/or stretchable, and or transparent electronic device.

Methods for annealing a metal foil layer to a glass layer, and/or for growing a native silicon layer in-situ therebetween. The annealing method includes applying an electrostatic (ES) field to the structure of the glass layer and the metal foil layer, with the metal foil layer positioned adjacent the glass layer, to electrostatically anneal them together. An electrostatic voltage of at least 1500 V may be applied. A seed crystal may be positioned between the glass layer and the metal foil layer prior to annealing. The method for growing a native metal (e.g., Si) layer in-situ may include applying an electrostatic voltage to the annealed structure with polarities reversed, at 1050 F. to 1100 F. Such conditions induce a redox reaction within the silica glass layer to reduce a portion of the silica, generating a layer of silicon between the glass layer and the metal foil layer.

A composite substrate has a carrier and a utility layer. The utility layer is attached to the carrier by means of a dielectric bonding layer and the carrier contains a radiation conversion material. Other embodiments relate to a semiconductor chip having such a composite substrate, a method for producing a composite substrate and a method for producing a semiconductor chip with a composite substrate.

One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a silicon-carbide (SiC) semiconductor material above the fin in the source and drain regions of a FinFET device. In this example, the method also includes performing a heating process so as to form a source/drain graphene contact from the silicon-carbide (SiC) semiconductor material in both the source and drain regions of the FinFET device and forming first and second source/drain contact structures that are conductively coupled to the source/drain graphene contact in the source region and the drain region, respectively, of the FinFET device.

A field effect transistor (FET) including a graphene layer as a carrier transporting channel is disclosed. The FET provides, on a substrate, a graphene layer, and electrodes of the source and drain on the graphene layer. The FET further provides a couple of gate electrodes and a supplemental electrode, where the former two gate electrodes are provided on a gate insulating film, while, the latter one is provided on the graphene layer and between two gate electrodes. The second gate electrode provided closer to the drain electrode has a gate length that is shorter than the gate length of the first gate electrode provided closer to the source electrode.

Low temperature epitaxial silicon deposition for forming the top source or drain regions of VTFET structures. The methods generally include epitaxially growing a silicon layer with a dopant at a temperature less 500 C. on a first surface and an additional surface to form a single crystalline silicon on the first surface and a polysilicon or amorphous silicon on the additional surface. The epitaxially grown silicon layer is then exposed to an etchant include HCl and germane at a temperature less than 500 C. for a period of time effective to selectively remove the polysilicon/amorphous silicon on the additional surface and form a germanium diffused region on and in an outer surface of the single crystalline silicon formed on the first surface.

A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.