Patent classifications
H01L21/0272
Semiconductor device manufacturing method and semiconductor device
A semiconductor device manufacturing method includes: forming an electrode including an Ni layer and an Au layer successively stacked on a semiconductor layer; forming a Ni oxide film by performing heat treatment to the electrode at a temperature of 350° C. or more to deposit Ni at least at a part of a surface of the Au layer and to oxidize the deposited Ni; and forming an insulating film in contact with the Ni oxide film and containing Si.
VACUUM CHANNEL TRANSISTOR STRUCTURES WITH SUB-10 NANOMETER NANOGAPS AND LAYERED METAL ELECTRODES
A technique relates to a semiconductor device. An emitter electrode and a collector electrode are formed in a dielectric layer such that a nanogap separates the emitter electrode and the collector electrode, a portion of the emitter electrode including layers. A channel is formed in the dielectric layer so as to traverse the nanogap. A top layer is formed over the channel so as to cover the channel and the nanogap without filling in the channel and the nanogap, thereby forming a vacuum channel transistor structure.
METHOD OF FABRICATING TRANSISTOR WITH SHORT GATE LENGTH BY TWO-STEP PHOTOLITHOGRAPHY
A method of fabricating transistors with short gate length by two-step photolithography is provided. This method utilizes the two-step photolithography by a stepper as well as controlling a first exposed position and a second exposed position to change the gate length.
Method and systems for coupling semiconductor substrates
Systems and methods may be provided for coupling together semiconductor devices. One or more of the semiconductor devices may be provided with an array of bump contacts formed in an etch back process. The bump contacts may be indium bumps. The indium bumps may be formed by depositing a sheet of indium onto a surface of a device substrate, depositing and patterning a layer of photoresist over the indium layer, and selectively etching the indium layer to the surface of the substrate using the patterned photoresist layer to form the indium bumps. The substrate may be an infrared detector substrate. The infrared detector substrate may be coupled to a readout integrated circuit substrate using the bumps.
NITRIDE SEMICONDUCTOR DEVICE
A nitride semiconductor device is disclosed. The semiconductor device is formed by a process that first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.
Method for making thin film transistor with nanowires as masks
A method of making a thin film transistor, the method includes: providing a semiconductor layer; arranging a first photoresist layer, a nanowire structure, a second photoresist layer on the semiconductor layer, wherein the nanowire structure includes a single nanowire; forming one opening in the first photoresist layer and the second photoresist layer to form an exposed surface, wherein a part of the nanowire is exposed and suspended in the opening; depositing a conductive film layer on the exposed surface using the nanowire structure as a mask, wherein the conductive film layer defines a nano-scaled channel, and the conductive film layer is divided into two regions, one region is used as a source electrode, and the other region is used as a drain electrode; forming an insulating layer on the semiconductor layer to cover the source electrode and the drain electrode, and locating a gate electrode on the insulating layer.
Methods of Manufacturing Semiconductor Devices
A semiconductor device and method of making a conductive connector is provided. In an embodiment an opening is formed within a photoresist by adjusting the center point of an in-focus area during the exposure process. Once the photoresist has been developed to form an opening, an after development baking process is utilized to reshape the opening. Once reshaped, a conductive material is formed into the opening to take on the shape of the opening.
Process of forming nitride semiconductor device
A process of forming a nitride semiconductor device is disclosed. The process first deposits a silicon nitride (SiN) film on a semiconductor layer by the lower pressure chemical vapor deposition (LPCVD) technique at a temperature, then, forming an opening in the SiN film for an ohmic electrode. Preparing a photoresist on the SiN film, where the photoresist provides an opening that fully covers the opening in the SiN film, the process exposes a peripheral area around the opening of the SiN film to chlorine (Cl) plasma that may etch the semiconductor layer to form a recess therein. Metals for the ohmic electrode are filled within the recess in the semiconductor layer and the peripheral area of the SiN film. Finally, the metals are alloyed at a temperature lower than the deposition temperature of the SiN film.
Redistribution Layers And Methods Of Fabricating The Same In Semiconductor Devices
A semiconductor structure includes a first passivation layer disposed over a metal line, a copper-containing RDL disposed over the first passivation layer, where the copper-containing RDL is electrically coupled to the metal line and where a portion of the copper-containing RDL in contact with a top surface of the first passivation layer forms an acute angle, and a second passivation layer disposed over the copper-containing RDL, where an interface between the second passivation layer and a top surface of the copper-containing RDL is curved. The semiconductor structure may further include a polymeric layer disposed over the second passivation layer, where a portion of the polymeric layer extends to contact the copper-containing RDL, a bump electrically coupled to the copper-containing RDL, and a solder layer disposed over the bump.
MOLECULAR LAYER ETCHING
A method of etching an organic or hybrid inorganic/organic material. The method etches molecular layer deposition coatings. An etching cycle comprises a first half reaction exposing the coating to a precursor. A second half reaction exposes a second precursor, removing or etching a portion of the coating.