H01L21/0272

FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE

A field effect transistor includes: a semiconductor region including a first inactive region, an active region, and a second inactive region arranged side by side in a first direction; a gate electrode, a source electrode, and a drain electrode on the active region; a gate pad on the first inactive region; a gate guard on and in contact with the semiconductor region, the gate guard being apart from the gate pad and located between an edge on the first inactive region side of the semiconductor region and the gate pad; a drain pad on the second inactive region; a drain guard on and in contact with the semiconductor region, the drain guard being apart from the drain pad and located between an edge on the second inactive region side of the semiconductor region and the drain pad; and a metal film electrically connected to the gate guard.

Method for manufacturing device

According to one embodiment, a method for manufacturing a device includes a first process, a second process, a third process, and a fourth process. The first process includes providing a structure body at a first surface of a substrate. The substrate is light-transmissive and has a second surface. A light transmissivity of the structure body is lower than a light transmissivity of the substrate. The second process includes providing a negative-type photoresist at the second surface. The third process includes irradiating the substrate with light to expose a portion of the photoresist. The light is irradiated in a first direction from the first surface toward the second surface. The light passes through the substrate. The fourth process includes developing the photoresist to remain the portion of the photoresist in a state of being adhered to the second surface and to remove other portion of the photoresist.

BACKPLANE FOR DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
20200273943 · 2020-08-27 ·

A method of manufacturing a backplane for a display device includes forming an insulation layer on a substrate, forming a pad electrode layer on the insulation layer, forming a photoresist pattern on the pad electrode layer in the pad region, etching the pad electrode layer and a portion of the insulation layer by the photoresist pattern as an etch-stop layer so as to simultaneously form a pad electrode and a side protection layer, the side protection layer covering a sidewall of the pad electrode, and stripping the photoresist pattern.

Preparation method for fully transparent thin film transistor

The present invention provides a preparation method for a fully-transparent thin film transistor, wherein a transparent conductive gate electrode layer of the fully-transparent thin film transistor is used as a photolithographic mask, a photoresist is exposed through a rear surface of a transparent substrate, the transparent substrate has a transmittance higher than 60% to an exposure light beam, and the transparent conductive gate electrode layer has a transmittance lower than 5% to the exposure light beam. In the preparation method for a fully-transparent thin film transistor provided by the present invention, by using a self-aligned technology, the process complexity and the feature size of the device can both be reduced.

Method of forming film
10741444 · 2020-08-11 · ·

In a method according to an exemplary embodiment, a substrate is prepared in a chamber. A patterned resist mask has been formed on a first region of the substrate. A surface of the substrate in a second region is exposed. A film is formed on the substrate in the chamber by sputtering. The film is formed on the substrate in a manner that particles emitted obliquely downward from a target are caused to be incident onto the substrate.

Electronic device, manufacturing method for electronic device, and electronic apparatus
10734495 · 2020-08-04 · ·

An electronic device includes, a semiconductor layer, a source region and a drain region provided with the semiconductor layer to be interposed therebetween, a gate insulation film on the semiconductor layer between the source region and the drain region, and a gate of a graphene on the gate insulation film. The gate insulation film induces doping of charges in the graphene.

Reactive ion etching assisted lift-off processes for fabricating thick metallization patterns with tight pitch

Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.

APPARATUS AND METHODS FOR ASYMMETRIC DEPOSITION OF METAL ON HIGH ASPECT RATIO NANOSTRUCTURES

Methods and apparatus for asymmetric deposition of a material on a structure formed on a substrate are provided herein. In some embodiments, a method for asymmetric deposition of a material includes forming a plasma from a process gas comprising ionized fluorocarbon (CxFy) particles, depositing an asymmetric fluorocarbon (CxFy) polymer coating on a first sidewall and a bottom portion of an opening formed in a first dielectric layer using angled CxFy ions, depositing a metal, metallic nitride, or metallic oxide on a second sidewall of the opening, and removing the CxFy polymer coating from the first sidewall and the bottom portion of the opening to leave an asymmetric deposition of the metal, metallic nitride, or metallic oxide on the structure.

Orthogonal patterning method

The present invention relates to a method for forming a layer, to be patterned, of an element by using a fluorinated material, which has orthogonality, and a solvent, the method comprising: a first step of printing with the fluorinated material so as to form, on a surface of a substrate, a mask template provided with an exposure part and a non-exposure part; a second step of coating the exposure part with a material to be patterned; a the third step of lifting-off the non-exposure part with the fluorinated solvent so as to form the layer to be patterned in the exposure part.

Method of manufacturing display apparatus and display apparatus manufactured using the same

A method of manufacturing a display apparatus includes preparing a substrate including a display area and a pad area outside of the display area, forming a sacrificial layer in the pad area, forming an encapsulation layer over the display area and the pad area, forming cracks in at least a portion of the encapsulation layer by increasing a volume of the sacrificial layer or by gasifying or evaporating at least a portion of the sacrificial layer, and removing at least a portion of the encapsulation layer in the pad area. A display apparatus is manufactured according to the manufacturing method.