A method of making a device includes providing a fluorinated material layer over the device substrate having one or more target areas for patterning. One or more lift-off structures are formed at least in part by developing a first pattern of one or more open areas in the fluorinated material layer in alignment with the one or more target areas by contact with a developing agent including a fluorinated solvent which dissolves the fluorinated material at a first rate. After patterning, the lift-off structures are removed by contact with a lift-off agent including a fluorinated solvent wherein the lift-off agent dissolves the fluorinated material at a second rate that is at least 150 nm/sec and higher than the first rate.

A tunable amorphous silicon layer for use with multilayer patterning stacks can be used to maximize transparency and minimize reflections so as to improve overlay metrology contrast. By increasing the hydrogen content in the amorphous silicon layer, the extinction coefficient (k) value and the refractive index (n) value can be decreased to desired values. Methods for improving overlay metrology contrast with the tunable amorphous silicon layer are disclosed.

In a method according to an exemplary embodiment, a substrate is prepared in a chamber. A patterned resist mask has been formed on a first region of the substrate. A surface of the substrate in a second region is exposed. A film is formed on the substrate in the chamber by sputtering. The film is formed on the substrate in a manner that particles emitted obliquely downward from a target are caused to be incident onto the substrate.

A method for fabricating a template includes providing a substrate having a first protrusion portion, forming, on the first protrusion portion of the substrate, a first film including a plurality of first pattern portions and a second pattern portion surrounding the first pattern portions and having a thickness thicker than the first pattern portions, covering at least a portion of the first film with a second film, removing the second pattern portion and exposing one or more of the first pattern portions by removing a portion of the second film from an upper surface of the first pattern by a first etching process, and forming a second protrusion portion by etching the first protrusion portion using the second film as a mask. The method further includes removing the first pattern portions and processing the first protrusion portion and the second protrusion portion by a second etching process.

Methods and related apparatus for depositing an ashable hard mask (AHM) on a substrate include pulsing a low frequency radio frequency component at a high power. Pulsing low frequency power may be used to increase the selectivity or reduce the stress of an AHM. The AHM may then be used to etch features into underlying layers of the substrate.

The present invention provides a preparation method for a fully-transparent thin film transistor, wherein a transparent conductive gate electrode layer of the fully-transparent thin film transistor is used as a photolithographic mask, a photoresist is exposed through a rear surface of a transparent substrate, the transparent substrate has a transmittance higher than 60% to an exposure light beam, and the transparent conductive gate electrode layer has a transmittance lower than 5% to the exposure light beam. In the preparation method for a fully-transparent thin film transistor provided by the present invention, by using a self-aligned technology, the process complexity and the feature size of the device can both be reduced.

According to an embodiment, a template is provided which includes a template substrate, and a device formation pattern and an alignment mark provided on a common surface of the template substrate. The alignment mark includes a refraction layer provided at a bottom of a first concave pattern provided on the template substrate, and an insulating layer filling the first concave pattern provided with the refraction layer.

A semiconductor substrate (1) has a front surface and a rear surface facing each other. A gate wiring (2) and first and second front surface electrodes (3,4) are provided on the front surface of the semiconductor substrate (1). The first and second front surface electrodes (3,4) are separated from each other by the gate wiring (2). An insulating film (7) covers the gate wiring (2). An electrode layer (8) is provided on the insulating film (7) and the first and second front surface electrodes (3,4) across the gate wiring (2). A rear surface electrode (9) is provided on the rear surface of the semiconductor substrate (1). A first plated electrode (10) is provided on the electrode layer (8). A second plated electrode (11) is provided on the rear surface electrode (9).

The present disclosure provides a method for manufacturing an array substrate. An ashing treatment is performed on the first photoresist pattern to remove the photoresist layer in the photoresist-partially-retained-region and to thin the photoresist layer in the photoresist-entirely-retained-region, so that a second photoresist pattern is generated. Thereafter, the passivation layer is etched using the second photoresist pattern as a mask to thin the passivation layer in the photoresist-partially-retained-region and to reduce roughness of the rough top surface in the photoresist-partially-retained-region. Therefore, process stability is raised.

The present disclosure provides a method for manufacturing an array substrate. An ashing treatment is performed on the first photoresist pattern to remove the photoresist layer in the photoresist-partially-retained-region and to thin the photoresist layer in the photoresist-entirely-retained-region, so that a second photoresist pattern is generated. Thereafter, the passivation layer is etched using the second photoresist pattern as a mask to thin the passivation layer in the photoresist-partially-retained-region and to reduce roughness of the rough top surface in the photoresist-partially-retained-region. Therefore, process stability is raised.