Methods and materials for growing TMD materials on substrates and making semiconductor devices are described. Metal contacts may be created prior to conducting a deposition process such as chemical vapor deposition (CVD) to grow a TMD material, such that the metal contacts serve as the seed/catalyst for TMD material growth. A method of making a semiconductor device may include conducting a lift-off lithography process on a substrate to produce a substrate having metal contacts deposited thereon in lithographically defined areas, and then growing a TMD material on the substrate by a deposition process to make a semiconductor device. Further described are semiconductor devices having a substrate with metal contacts deposited thereon in lithographically defined areas, and a TMD material on the substrate, where the TMD material is a continuous, substantially uniform monolayer film between and on the metal contacts, where the metal contacts are chemically bonded to the TMD material.

Various embodiments of the present technology generally relate to semiconductor device architectures and manufacturing techniques. More specifically, some embodiments of the present technology relate to large area metrology and process control for anisotropic chemical etching. Catalyst influenced chemical etching (CICE) can be used to create high aspect ratio semiconductor structures with dimensions in the nanometer to millimeter scale with anisotropic and smooth sidewalls. However, all aspects of the CICE process must be compatible with the equipment used in semiconductor fabrication facilities today, and they must be scalable to enable wafer scale processing with high yield and reliability. This invention relates to metrology and control of etch and CMOS compatible methods of patterning the catalyst and removing it without damaging the etched structures.

A process for making an interconnect of a group III-V semiconductor device includes the steps of applying a positive photoresist layer and an image-reversible photoresist layer, subjecting the image-reversible photoresist and positive photoresist layers to patternwise exposure, subjecting the image-reversible photoresist layer to image reversal bake, subjecting the image-reversible photoresist and positive photoresist layers to flood exposure, subjecting the image-reversible photoresist and positive photoresist layers to development, depositing a diffusion barrier layer, depositing a copper layer, and removing the image-reversible photoresist and positive photoresist layers.

A process for manufacturing a HEMT device includes forming a conductive region on a work body having a semiconductive heterostructure. To obtain the conductive region, a first reaction region having carbon is formed on the heterostructure and a metal stack is formed having a second reaction region in contact with the first reaction region. The work body is annealed, so that the first reaction region reacts with the second reaction region, thus forming an interface portion of the conductive region. The interface portion is of a compound having carbon and is in ohmic contact with the semiconductive hetero structure.

An enhancement mode high electron-mobility transistor (HEMT) device includes a semiconductor body having a top surface and including a heterostructure configured to generate a two-dimensional electron gas, 2DEG. The HEMT device includes a gate structure which extends on the top surface of the semiconductor body, is biasable to electrically control the 2DEG and includes a functional layer and a gate contact in direct physical and electrical contact with each other. The gate contact is of conductive material and the functional layer is of two-dimensional semiconductor material and includes a first doped portion with P-type electrical conductivity, which extends on the top surface of the semiconductor body and is interposed between the semiconductor body and the gate contact along a first axis.

A touch panel and a method of manufacturing the touch panel are provided. The touch panel includes a substrate comprising a wiring area and a sensor area, a sensing pattern located on a surface of the substrate in the sensor area, and a wiring line located on the surface of the substrate in the wiring area and electrically connected to the sensing pattern. The sensing pattern includes a plurality of first fine metal lines arranged irregularly in a mesh, and a first photosensitive layer pattern residue located between at least two of the first fine metal lines.

A serigraphy method for producing a soulder bump on the front surface of a substrate includes: forming a film on the front surface, forming an opening in the film, filling the opening with a souldering material, and removing the film. Forming a film on the front surface is preceded by the formation of an intermediate layer between the film and the front surface, the intermediate layer being adapted to exhibit a force of adherence at one and/or the other interface formed with the first front surface and the film lower than the force of adherence that can be formed between the film and the first front surface.

After a plurality of trenches is formed in an SOI substrate, a side surface of the insulating layer is retreated from a side surface of the semiconductor layer and a side surface of the semiconductor substrate. Next, the side surface of the insulating layer is covered with an organic film and also the side surface of the semiconductor layer is exposed from the organic film by performing an anisotropic etching process to the organic film embedded into an inside of each of the plurality of trenches. Next, each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate is approached to the side surface of the insulating layer by performing an isotropic etching process. Further, after the organic film is removed, an oxidation treatment is performed to each of the side surface of the semiconductor layer and the side surface of the semiconductor substrate.

A method of fabricating a gate with a mini field plate includes forming a dielectric passivation layer over an epitaxy layer on a substrate, coating the dielectric passivation layer with a first resist layer, etching the first resist layer and the dielectric passivation layer to form a first opening in the dielectric passivation layer, removing the first resist layer; and forming a tri-layer gate having a gate foot in the first opening, the gate foot having a first width, a gate neck extending from the gate foot and extending for a length over the dielectric passivation layer on both sides of the first opening, the gate neck having a second width wider than the first width of the gate foot, and a gate head extending from the gate neck, the gate head having a third width wider than the second width of the gate neck.

The present disclosure provides a coating method and a coating system. The coating method comprises: providing a substrate, and dropping a first liquid onto the substrate; dropping, onto the first liquid, a second liquid which is immiscible with the first liquid and has a density greater than that of the first liquid; and rotating the substrate, such that the first liquid is diffused on the surface of the substrate, and the second liquid is diffused on the surface of the first liquid.