A method of forming a semiconductor device comprises patterning a mask material adjacent to an array of transistors, forming an electrically conductive material between adjacent portions of the patterned mask material, forming an additional mask material over the patterned mask material to form a mask structure, the additional mask material having an arcuate cross-sectional shape, removing a portion of the additional mask material to reduce a spacing between adjacent portions of the additional mask material, and forming capacitor structures in openings between the mask structure. Additional methods of forming a semiconductor device, and related semiconductor devices and related systems are also disclosed.

A method for selectively etching a metal component of a workpiece comprises: forming a hard mask over the metal component; and etching the metal component using an etchant solution, whereby the hard mask controls the etching; wherein the etchant solution is a basic etchant solution; and wherein the workpiece includes a semiconductor component comprising a material of Formula 1:

InAs.sub.xSb.sub.1-x

wherein x is in the range 0 to 1. It has surprisingly been found that basic etchants do not damage the semiconductor material. Another aspect provides the use of a basic etchant to etch aluminium selectively in the presence of a semiconductor comprising a material of Formula 1, where x is in the range 0 to 0.25.

A support substrate including a plurality of channels on a front side is provided. A cover layer is formed by anisotropically depositing a sacrificial cover material over the plurality of channels. Cavities laterally extend within the plurality of channels underneath a horizontally extending portion of the cover layer. An encapsulation layer is conformally deposited. First semiconductor devices, first metal interconnect structures, and first bonding pads are formed over a top surface of the encapsulation layer. A device substrate with second bonding pads is provided. The second bonding pads are bonded with the first bonding pads to form a bonded assembly. Peripheral portions of the encapsulation layer are removes and peripheral portions of the cover layer are physically exposed. The cover layer is removed employing an isotropic etch process by propagating an isotropic etchant through the cavities to separate the support substrate from the bonded assembly.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A semiconductor structure includes a semiconductor substrate, a metal layer, an interlayer dielectric (ILD) layer. The metal layer is disposed over the semiconductor substrate. The ILD layer is over the semiconductor substrate and laterally surrounding the metal layer, in which the ILD layer has a first portion in contact with a first sidewall of the metal layer and a second portion in contact with a second sidewall of the metal layer opposite to the first sidewall of the metal layer, and a width of the first portion of the ILD layer decreases as a distance from the semiconductor substrate increases.

The disclosed technology generally relates to forming metallization structures for integrated circuit devices by plating, and more particularly to plating metallization structures that are thicker than masking layers used to define the metallization structures. In one aspect, a method of metallizing an integrated circuit device includes plating a first metal on a substrate in a first opening formed through a first masking layer, where the first opening defines a first region of the substrate, and plating a second metal on the substrate in a second opening formed through a second masking layer, where the second opening defines a second region of the substrate. The second opening is wider than the first opening and the second region encompasses the first region of the substrate.

A method for forming a lift-off mask structure includes providing a substrate body, depositing a layer of bottom anti-reflective coating, BARC, over a surface of the substrate body, and depositing a layer of photosensitive resist over the BARC layer. The method further includes exposing the resist layer to electromagnetic radiation through a photomask, and forming the lift-off mask structure by applying a developer for selectively removing a portion of the BARC layer and of the resist layer such that an underlying portion of the surface of the substrate body is exposed.

A method is provided. A sacrificial layer is formed over a semiconductor substrate. An etching process is performed to form an opening in the sacrificial layer. The etching process includes a first cycle and a second cycle performed after the first cycle, and each of the first cycle and the second cycle includes applying a passivation gas and an etchant gas over the sacrificial layer, and performing an ionized gas bombardment on the sacrificial layer after applying the passivation gas and the etchant gas over the sacrificial layer. The passivation gas is applied at a first flow rate in the first cycle and is applied at a second flow rate in the second cycle, and the first flow rate is higher than the second flow rate.

Provided are a cleaning method and cleaning device for cleaning with micro/nano-bubbles, with which a simple method of spraying a treatment solution containing micro/nano-bubbles onto a substrate to be processed makes it possible to efficiently and reliably peel off residual resist or remove contaminants from the substrate, while reducing an environmental load.

This cleaning method is characterized in that, with respect to a substrate to be treated to which a resist film has adhered onto the substrate or a substrate to be treated to which the surface thereof has been contaminated with a metal or metal compounds, the resist film is peeled off or the metals or metal compounds are removed by spraying onto the substrate to be treated a treatment solution containing gaseous micro/nano-bubbles and having a temperature maintained at 30 C. to 90 C., the mean particle size of the micro/nano-bubbles when measured by an ice embedding method using a cryo-transmission electron microscope being 100 nm or smaller, preferably 30 nm or smaller, and also preferably the density of such bubbles being 10.sup.8 or more bubbles per 1 mL.

Lift-off methods for fabricating metal line patterns on a substrate are provided. For example, a method to fabricate a device includes forming a sacrificial layer on a substrate and forming a photoresist mask over the sacrificial layer, isotropically etching a portion of the sacrificial layer exposed through an opening of the photoresist mask to form an undercut region in the sacrificial layer below the photoresist mask, wherein the undercut region defines an overhang structure, and anisotropically etching a portion of the sacrificial layer exposed through the opening of the photoresist mask to form an opening through the sacrificial layer down to the substrate. Metallic material is deposited to cover the photoresist mask and to at least partially fill the opening formed in the sacrificial layer without coating the overhang structure with metallic material. The sacrificial layer is dissolved to lift-off the metallic material covering the photoresist mask.