H01L21/0332

Method of manufacturing semiconductor device having a structure pattern having a plurality of trenches

A method of manufacturing a semiconductor device includes forming a base layer on a substrate. A structure layer is Conned on the base layer. The structure layer includes at least one material layer. A structure pattern is formed on the base layer. The structure pattern includes a first trench extending in a first direction and a second trench having a cross portion extending in a second direction that is perpendicular to the first direction. The second trench is connected to the first trench. The structure pattern further includes a base pattern having a recess portion recessed downward from a surface of the base layer at the cross portion of the second trench.

Film stack for lithography applications

Methods for forming a film stack comprising a hardmask layer and etching such hardmask layer to form features in the film stack are provided. The methods described herein facilitate profile and dimension control of features through a proper profile management scheme formed in the film stack. In one or more embodiments, a method for etching a hardmask layer includes forming a hardmask layer on a substrate, where the hardmask layer contains a metal-containing material containing a metal element having an atomic number greater than 28, supplying an etching gas mixture to the substrate, and etching the hardmask layer exposed by a photoresist layer.

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A semiconductor device includes a substrate, first and second semiconductor strips, a dummy fin structure, first and second channel layers, a gate structure, and crystalline and amorphous hard mask layers. The first and second semiconductor strips extend upwardly from the substrate and each has a length extending along a first direction. The dummy fin structure is laterally between the first and second semiconductor strips. The first and second channel layers extend in the first direction above the first and second semiconductor strips and are arranged in a second direction substantially perpendicular to the substrate. The crystalline hard mask layer extends upwardly from the dummy fin structure and has an U-shaped cross section. The amorphous hard mask layer is in the crystalline hard mask layer. The amorphous hard mask layer has an U-shaped cross section conformal to the U-shaped cross section of the crystalline hard mask layer.

HETEROGENEOUS METAL LINE COMPOSITIONS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first plurality of conductive interconnect lines in and spaced apart by a first ILD layer, wherein individual ones of the first plurality of conductive interconnect lines comprise a first conductive barrier material along sidewalls and a bottom of a first conductive fill material. A second plurality of conductive interconnect lines is in and spaced apart by a second ILD layer above the first ILD layer, wherein individual ones of the second plurality of conductive interconnect lines comprise a second conductive barrier material along sidewalls and a bottom of a second conductive fill material, wherein the second conductive fill material is different in composition from the first conductive fill material.

Computer storage medium to perform a substrate treatment method using a block copolymer containing a hydrophilic and hydrophobic copolymers

A substrate treatment method of treating a substrate using a block copolymer containing a hydrophilic polymer and a hydrophobic polymer, includes: a resist pattern formation step of forming a predetermined resist pattern by a resist film on the substrate; a thin film formation step of forming a thin film for suppressing deformation of the resist pattern on a surface of the resist pattern; a block copolymer coating step of applying a block copolymer to the substrate after the formation of the thin film; and a polymer separation step of phase-separating the block copolymer into the hydrophilic polymer and the hydrophobic polymer.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
20230102166 · 2023-03-30 ·

A method of manufacturing a semiconductor device includes forming a protective layer over a substrate. The hydrophilicity of the protective layer is reduced. A resist layer is formed over the protective layer, and the resist layer is patterned.

DEPOSITION OF BORON NITRIDE FILMS USING HYDRAZIDO-BASED PRECURSORS
20230098689 · 2023-03-30 ·

A method of forming high quality a-BN layers. The method includes use of a precursor chemistry that is particularly suited for use in a cyclical deposition process such as in chemical vapor deposition (CVD), atomic layer deposition (ALD), and the like. In brief, new methods are described of forming boron nitride (BN) layers from precursors capable of growing amorphous BN (a-BN) films by CVD, ALD, or the like. In some cases, the precursor is or includes a borane adduct of hydrazine or a hydrazine derivative.

HIGHLY ETCH SELECTIVE AMORPHOUS CARBON FILM

Methods and techniques for deposition of amorphous carbon films on a substrate are provided. In one example, the method includes depositing an amorphous carbon film on an underlayer positioned on a susceptor in a first processing region. The method further includes implanting a dopant or the inert species into the amorphous carbon film in a second processing region. The implant species, energy, dose & temperature in some combination may be used to enhance the hardmask hardness. The method further includes patterning the doped amorphous carbon film. The method further includes etching the underlayer.

PLASMA ETCHING OF MASK MATERIALS

Exemplary etching methods may include forming a plasma of a fluorine-containing precursor to produce plasma effluents. A first bias frequency may be applied while forming the plasma. The methods may include contacting a substrate housed in a processing region of a semiconductor processing chamber with the plasma effluents. The substrate may be or include a photomask. The methods may include etching a first layer of the photomask. Etching the first layer of the photomask may expose a second layer of the photomask. The methods may include adjusting the first bias frequency to a second bias frequency while maintaining the plasma of the fluorine-containing precursor. The methods may include etching the second layer of the photomask.

PROCESSES TO DEPOSIT AMORPHOUS-SILICON ETCH PROTECTION LINER
20220351982 · 2022-11-03 ·

Embodiments of the present disclosure generally relate to fabricating electronic devices, such as memory devices. In one or more embodiments, a method for forming a device includes forming a film stack on a substrate, where the film stack contains a plurality of alternating layers of oxide layers and nitride layers and has a stack thickness, and etching the film stack to a first depth to form a plurality of openings between a plurality of structures. The method includes depositing an etch protection liner containing amorphous-silicon on the sidewalls and the bottoms of the structures, removing the etch protection liner from at least the bottoms of the openings, forming a plurality of holes by etching the film stack in the openings to further extend each bottom of the openings to a second depth of the hole, and removing the etch protection liner from the sidewalls.