A substrate treatment method for treating a substrate, includes: applying a coating solution containing an organometallic complex, a solvent, and an additive to the substrate to form a solution film of the coating solution; heating the substrate on which the solution film of the coating solution has been formed, to form an organic constituent-containing metal oxide film being a metal oxide film containing an organic constituent contained in the additive; performing dry etching using the organic constituent-containing metal oxide film as a mask; removing the organic constituent in the organic constituent-containing metal oxide film after the dry etching; and removing, by wet etching, a film obtained by removing the organic constituent from the organic constituent-containing metal oxide film.

A method of forming a semiconductor device includes forming a mask layer over a substrate and forming an opening in the mask layer. A gap-filling material is deposited in the opening. A plasma treatment is performed on the gap-filling material. The height of the gap-filling material is reduced. The mask layer is removed. The substrate is patterned using the gap-filling material as a mask.

A method includes forming a tri-layer. The tri-layer includes a bottom layer; a middle layer over the bottom layer; and a top layer over the middle layer. The top layer includes a photo resist. The method further includes removing the top layer; and removing the middle layer using a chemical solution. The chemical solution is free from potassium hydroxide (KOH), and includes at least one of a quaternary ammonium hydroxide and a quaternary ammonium fluoride.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An isolation structure surrounds a lower fin portion, the isolation structure comprising an insulating material having a top surface, and a semiconductor material on a portion of the top surface of the insulating material, wherein the semiconductor material is separated from the fin. A gate dielectric layer is over the top of an upper fin portion and laterally adjacent the sidewalls of the upper fin portion, the gate dielectric layer further on the semiconductor material on the portion of the top surface of the insulating material. A gate electrode is over the gate dielectric layer.

A method for forming a nanopore device includes providing a sapphire substrate and forming oxide layers on the front and back sides of the sapphire substrate. The oxide layer on the back is patterned to form an etch mask. The method also includes performing a crystalline orientation dependent wet anisotropic etch on the backside of the sapphire substrate using the etch mask to form a cavity having sloped sides to expose a portion of the first oxide layer. A silicon nitride membrane layer is formed on the oxide layer on the front side of the sapphire substrate. Next, the exposed portion of the oxide layer in the cavity is removed to cause the exposed portion of the silicon nitride membrane layer to be suspended over the cavity in the sapphire substrate. Subsequently, an opening is formed in the suspended portion of the silicon nitride membrane layer to form the nanopore.

Methods for depositing an amorphous carbon layer onto a substrate, including over previously formed layers on the substrate, use a plasma-enhanced chemical vapor deposition (PECVD) process. In particular, the methods utilize a combination of RF AC power and pulsed DC power to create a plasma which deposits an amorphous carbon layer with a high ratio of sp3 (diamond-like) carbon to sp2 (graphite-like) carbon. The methods also provide for lower processing pressures, lower processing temperatures, and higher processing powers, each of which, alone or in combination, may further increase the relative fraction of sp3 carbon in the deposited amorphous carbon layer. As a result of the higher sp3 carbon fraction, the methods provide amorphous carbon layers having improved density, rigidity, etch selectivity, and film stress as compared to amorphous carbon layers deposited by conventional methods.

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

Embodiments disclosed herein include methods of depositing a metal oxo photoresist using dry deposition processes. In an embodiment, the method comprises forming a first metal oxo film on the substrate with a first vapor phase process including a first metal precursor vapor and a first oxidant vapor, and forming a second metal oxo film over the first metal oxo film with a second vapor phase process including a second metal precursor vapor and a second oxidant vapor.

A method of fabricating a semiconductor device includes forming a first shallow trench isolation structure in a first region of a substrate and second shallow trench isolation structures in a second region of the substrate. The method also includes forming a mask layer over the substrate, the first shallow trench isolation structure, and the second shallow trench isolation structures. The method further includes etching the mask layer and second shallow trench isolation structures in the second region sequentially to form a semiconductor protrusion between the second shallow trench isolation structures.

In one exemplary embodiment, a method for forming a pattern includes (a) forming, on a substrate, a first pattern having an opening and containing a first material, (b) forming a filling portion in the opening, the filling portion containing a second material different from the first material, and (c) removing the first pattern so that the filling portion remains as a second pattern inverted with respect to the first pattern. At least one of the first material or the second material contains tin.