An exemplary method of preparing nitrogen-doped graphene whereby it is possible to synthesize graphene having an improved surface coverage and a uniform single layer, and to prepare high quality graphene in a large area. In addition, an aromatic compound containing nitrogen can be used as a carbon source and nitrogen-doped graphene can be thus synthesized as nitrogen doped in the synthesis process. It is possible to control the electrical properties of graphene depending on the nitrogen doping.

A PERC solar cell capable of improving photoelectric conversion efficiency and a preparation method thereof are provided. The solar cell consecutively includes, from the bottom up, a rear silver electrode (1), a rear aluminum field (2), a rear silicon nitride film (3), a rear aluminum oxide film (4), P-type silicon (5), N-type silicon (6), a front silicon nitride film (7), and a front silver electrode (8). The rear aluminum field (2) is connected to the P-type silicon (5) via a rear aluminum strip (10). The P-type silicon (5) is a silicon wafer of the cell. The N-type silicon (6) is an N-type emitter formed by diffusion via the front surface of the silicon wafer. The front silicon nitride film (7) is deposited on the front surface of the silicon wafer. The rear aluminum oxide film (4) is deposited on the rear surface of the silicon wafer. The rear aluminum oxide film (3) is deposited after the front silicon nitride film (7) is deposited on the silicon wafer, and the rear surface of the silicon wafer is washed before depositing the rear aluminum oxide film (3). The cell can significantly improves passivation effect of the rear aluminum oxide film and improve the open-circuit voltage and short-circuit current of the cell, thereby increasing photoelectric conversion efficiency of the cell.

Techniques for forming nanoribbon or bulk graphene-based SPR sensors are provided. In one aspect, a method of forming a graphene-based SPR sensor is provided which includes the steps of: depositing graphene onto a substrate, wherein the substrate comprises a dielectric layer on a conductive layer, and wherein the graphene is deposited onto the dielectric layer; and patterning the graphene into multiple, evenly spaced graphene strips, wherein each of the graphene strips has a width of from about 50 nanometers to about 5 micrometers, and ranges therebetween, and wherein the graphene strips are separated from one another by a distance of from about 5 nanometers to about 50 micrometers, and ranges therebetween. Alternatively, bulk graphene may be employed and the dielectric layer is used to form periodic regions of differing permittivity. A testing apparatus and method of analyzing a sample using the present SPR sensors are also provided.

An optoelectronic semiconductor chip including a semiconductor layer sequence containing a phosphide compound semiconductor material, wherein the semiconductor layer sequence includes a p-type semiconductor region, an n-type semiconductor region and an active layer disposed between the p-type semiconductor region and the n-type semiconductor region, a current spreading layer including a transparent conductive oxide adjoining the p-type semiconductor region, and a metallic p-connection layer at least regionally adjoining the current spreading layer, wherein the p-type semiconductor region includes a p-contact layer adjoining the current spreading layer, the p-contact layer contains GaP doped with C, a C dopant concentration in the p-contact layer is at least 5*10.sup.19 cm.sup.3, and the p-contact layer is less than 100 nm thick.

The present invention relates to a method for assembling molecules on the surface of a two-dimensional material formed on a substrate, the method comprises: forming a spacer layer comprising at least one of an electrically insulating compound or a semiconductor compound on the surface of the two-dimensional material, depositing molecules on the spacer layer, annealing the substrate with spacer layer and the molecules at an elevated temperature for an annealing time duration, wherein the temperature and annealing time are such that at least a portion of the molecules are allowed to diffuse through the spacer layer towards the surface of the two-dimensional material to assemble on the surface of the two-dimensional material. The invention also relates to an electronic device.

A laminated body of an embodiment includes: a silicon layer; a first beryllium oxide layer on the silicon layer; and a diamond semiconductor layer on the first beryllium oxide layer.

An enhanced symmetric multicycle rapid thermal annealing process for removing defects and activating implanted dopant impurities in a III-nitride semiconductor sample. A sample is placed in an enclosure and heated to a temperature T.sub.1 under an applied pressure P.sub.1 for a time t.sub.1. While the heating of the sample is maintained, the sample is subjected to a series of rapid laser irradiations under an applied pressure P.sub.2 and a baseline temperature T.sub.2. Each of the laser irradiations heats the sample to a temperature T.sub.max above its thermodynamic stability limit. After a predetermined number of temperature pulses or a predetermined period of time, the laser irradiations are stopped and the sample is brought to a temperature T.sub.3 and held at T.sub.3 for a time t.sub.3 to complete the annealing.

An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.

Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A plurality of channel layers are arranged in a layer stack, and a source/drain region is connected with the plurality of channel layers. A gate structure includes a plurality of sections that respectively surround the plurality of channel layers. The plurality of channel layers contain a two-dimensional semiconducting material.

An apparatus and method, the apparatus comprising: at least one charged substrate (3); a channel of two dimensional material (5); and at least one floating electrode (7A-C) wherein the floating electrode comprises a first area (10A-C) adjacent the at least one charged substrate, a second area (11A-C) adjacent the channel of two dimensional material and a conductive interconnection (9A-C) between the first area and the second area wherein the first area is larger than the second area and wherein the at least one floating electrode is arranged to control the level of doping within the channel of two dimensional material.