Disclosed is a graphene transistor using graphene as a channel region and a logic device using the same. A doping metal layer is provided over a graphene channel of the graphene transistor. The doping metal layer has a work function higher or lower than that of the graphene. When the doping metal layer has a work function lower than that of the graphene, the graphene, which is below the doping metal layer, is doped with an n-type. Also, when the doping metal layer has a work function higher than that of the graphene, the graphene, which is below the doping metal layer, is doped with a p-type. As described above, various aspects of junction may be implemented in the graphene channel, and three states may be obtained from a single transistor.

An apparatus comprising: pyroelectric material; an electric field sensor; a first conductive electrode comprising a first area adjacent the pyroelectric material; a second conductive electrode comprising a second area adjacent the electric field sensor; and a conductive interconnection between the first conductive electrode and the second conductive electrode, wherein the first area of the first conductive electrode is larger than the second area of the second conductive electrode.

A semiconductor device according to an embodiment includes an i-type or a p-type first diamond semiconductor layer, an n-type second diamond semiconductor layer provided on the first diamond semiconductor layer, a mesa structure and an n-type first diamond semiconductor region provided on the side surface. The mesa structure includes the first diamond semiconductor layer, the second diamond semiconductor layer, a top surface with a plane orientation of 10 degrees or less from a {100} plane, and a side surface inclined by 20 to 90 degrees with respect to a direction of <011>20 degrees from the {100} plane. The first diamond semiconductor region is in contact with the second diamond semiconductor layer and has an n-type impurity concentration lower than an n-type impurity concentration of the second diamond semiconductor layer.

An exemplary method of preparing nitrogen-doped graphene whereby it is possible to synthesize graphene having an improved surface coverage and a uniform single layer, and to prepare high quality graphene in a large area. In addition, an aromatic compound containing nitrogen can be used as a carbon source and nitrogen-doped graphene can be thus synthesized as nitrogen doped in the synthesis process. It is possible to control the electrical properties of graphene depending on the nitrogen doping.

A method for manufacturing a functionalized graphene structure includes preparing a substrate having a graphene layer, forming an organic linker layer by providing an organic linker on the graphene layer, and forming a dopant layer by providing a dopant material including a metal on the organic linker layer. The organic linker layer and the dopant layer are formed in-situ.

An active cell region, an edge termination region surrounding the active cell region and an intermediate region located at an intermediate position between these regions are provided, the active cell region has a trench gate type MOS structure on a top side, and a vertical structure on a bottom side includes a p-collector layer, an n-buffer layer on the p-collector layer, and an n-drift layer on the n-buffer layer, the n-buffer layer has a first buffer portion provided on the p-collector layer side, and a second buffer portion provided on the n-drift layer side, the peak impurity concentration of the first buffer portion is higher than the peak impurity concentration of the second buffer portion, and the impurity concentration gradient on the n-drift layer side of the second buffer portion is gentler than the impurity concentration gradient on the n-drift layer side of the first buffer portion.

A semiconductor rectifying device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a filling structure, an upper electrode, a guard ring, and a guard layer. The epitaxial layer defines a plurality of trenches thereon. The filling structure includes an insulating material formed on the inner surface of the trench and a conductive material filled in the trench. A doped region of a second conductivity type is formed in the surface of the epitaxial layer between the filling structures. A method of manufacturing a semiconductor rectifying device includes forming an epitaxial layer of a first conductivity type on a substrate of the first conductivity type, defining a plurality of trenches on the epitaxial layer, forming a plurality of filling structures in the plurality of trenches, and forming a doped region in the epitaxial layer between the filling structures.

A method of manufacturing an integrated circuit (IC) includes forming a first active region in a first cell. The method includes forming a plurality of second active regions in a second cell, wherein the second cell abuts the first cell. The method includes forming a third active region in a third cell, wherein the second cell is between the first cell and the third cell, and a height of the second cell is different from a height of the first cell or the third cell. The method includes forming a plurality of gate structures extending across each of the first active region, the plurality of second active regions, and the third active region. The method includes removing a first portion of a first gate structure at an interface between the first cell and the second cell between the first active region and the plurality of second active regions.

A polycrystalline CVD diamond material comprising a surface having a surface roughness R.sub.q of less than 5 nm, wherein said surface is damage free to the extent that if an anisotropic thermal revealing etch is applied thereto, a number density of defects revealed by the anisotropic thermal revealing etch is less than 100 per mm.sup.2.

A homoepitaxial, ultrathin tunnel barrier-based electronic device in which the tunnel barrier and transport channel are made of the same materialgraphene.