Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Techniques described herein generally relate to etching graphene. The techniques can include disposing graphene on a patterned substrate, applying a resist to the graphene on the patterned substrate, curing the resist, and etching exposed portions of the graphene. Graphene composites including patterned substrates, graphene disposed on the patterned substrate, and a resist disposed on the graphene, are disclosed. Systems configured to perform the methods and/or make the graphene composites are also disclosed.

The invention provides a recess structure for print deposition process and manufacturing method thereof. By disposing the dam (2) enclosing the recess (3) as comprising at least two stacked branch dam layers, and increasing the contact angle between the inclined inner circumferential surface of recess (3) enclosed by the branch dam layers and ink in a layer-by-layer manner, to limit height the ink able to climb on the inclined inner circumferential surface of the recess (3), the invention can improve the thickness uniformity of the organic functional layers printed in the recess and the photoelectric properties of organic functional layers. The recess (3) fabricated by the manufacturing method can limit height the ink able to climb on inclined inner circumferential surface of the recess (3) to improve the thickness uniformity of the organic functional layers printed in the recess and the photoelectric properties of organic functional layers.

A neuroelectric sensor and stimulator system includes a first antenna, a reader coupled to the first antenna for transmitting stimulation controls and power to a second antenna, and for receiving sensor data transmitted from the second antenna via the first antenna, and at least one neuroelectric sensor stimulator array including the second antenna, a rectifier coupled to the second antenna for extracting power transmitted from the first antenna, a controller coupled to the second antenna for decoding controls transmitted from the first antenna to the second antenna for the neuroelectric sensor stimulator array, a plurality of sensors, a multiplexer coupled to the controller and to the plurality of sensors for selecting a single sensor, and a plurality of stimulators coupled to the controller for stimulating neurons, wherein the rectifier, the controller, the plurality of sensors, the multiplexer, and the plurality of stimulators include graphene.

Graphite-based devices with a reduced characteristic dimension and methods for forming such devices are provided. One or more thin films are deposited onto a substrate and undesired portions of the deposited thin film or thin films are removed to produce processed elements with reduced characteristic dimensions. Graphene layers are generated on selected processed elements or exposed portions of the substrate after removal of the processed elements. Multiple sets of graphene layers can be generated, each with a different physical characteristic, thereby producing a graphite-based device with multiple functionalities in the same device.

Structures and methods for forming a patterned graphene layer on a substrate. One such method includes forming at least one patterned structure of a carbide-forming metal or metal-containing alloy on a substrate, applying a layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy on the substrate, heating the layer of graphene on top of the at least one patterned structure of a carbide-forming metal or metal-containing alloy in an environment to remove graphene regions proximate to the at least one patterned structure of a carbide-forming metal or metal-containing alloy, and removing the at least one patterned structure of a carbide-forming metal or metal-containing alloy to produce a patterned graphene layer on the substrate, wherein the patterned graphene layer on the substrate provides carrier mobility for electronic devices.

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.

A method for patterning a piece of carbon nanomaterial. The method comprises generating a first light pulse sequence with first light pulse sequence property values, the first light pulse sequence comprising at least one light pulse and exposing a first area of the piece of carbon nanomaterial to said first light pulse sequence in a first process environment having a first oxygen content, without exposing at least part of the piece of carbon nanomaterial to said first light pulse sequence. In this way, the method comprises oxidizing locally, in the first area, at least some carbon atoms of the piece of carbon nanomaterial in such a way that at most 10% of the carbon atoms of the first area are removed from the first area; thereby patterning the first area of the piece of carbon nanomaterial. In addition a processed piece of carbon nanomaterial.

An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate and an upper surface, an active area, a substrate opening in the semiconductor substrate that is partially defined by a recessed surface, and a thermally conductive layer disposed over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate within the active area. A method for fabricating the semiconductor device includes defining an active area, forming a gate electrode over a channel in the active area, forming a source electrode and a drain electrode in the active area on opposite sides of the gate electrode, etching a substrate opening in the semiconductor substrate that is partially defined by the recessed surface, and depositing a thermally conductive layer over the semiconductor substrate that extends between the recessed surface and a portion of the semiconductor substrate over the channel.