There is provided a method of manufacturing a transistor, the method comprising: (a) providing a substrate having a semiconductor surface; (b) providing a graphene layer structure on a first portion of the semiconductor surface, wherein the graphene layer structure has a thickness of n graphene monolayers, wherein n is at least 2; (c) etching a first portion of the graphene layer structure to reduce the thickness of the graphene layer structure in said first portion to from n−1 to 1 graphene monolayers; (d) forming a layer of dielectric material on the first portion of the graphene layer structure; and (e) providing: a source contact on a second portion of the graphene layer structure; a gate contact on the layer of dielectric material; and a drain contact on a second portion of the semiconductor surface of the substrate.

The present invention provides a method of manufacturing a graphene transistor 101, the method comprising: (a) providing a substrate having a substantially flat surface, wherein the surface comprises an insulating region 110 and an adjacent semiconducting region 105; (b) forming a graphene layer structure 115 on the surface, wherein the graphene layer structure is disposed on and across a portion of both the insulating region and the adjacent semiconducting region; (c) forming a layer of dielectric material 120 on a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and (d) providing: a source contact 125 on a portion of the graphene layer structure which is itself disposed on the insulating region 110; a gate contact 130 on the layer of dielectric material 120 and above a portion of the graphene layer structure which is itself disposed on the semiconducting region 105; and a drain contact 135 on the semiconducting region 105 of the substrate surface.

The present application discloses a method for forming a recess, which comprises the following steps: step 1: performing a dry etching process to a silicon substrate to form a U-shaped or ball-shaped recess; step 2: performing second etching to the recess by introducing HCl and GeH.sub.4 reaction gases in an epitaxial process chamber to form diamond-shaped recess. The present application further discloses a method for forming a recess and filling the recess with an epitaxial layer in situ. The disclosed etching changes U-shaped or ball-shaped reaction recess diamond-shaped recess by including reaction gases in the epitaxial process chamber, which is conducive to realizing the in-situ epitaxial filling process. This method reduces steps in the process loop of forming embedded epitaxial layer, thus decreasing defects from the process.

Methods for etching features into carbon material using a metal-doped carbon-containing hard mask to reduce and eliminate redeposition of silicon-containing residues are provided herein. Methods involve depositing a metal-doped carbon-containing hard mask over the carbon material prior to etching the carbon material, patterning the metal-doped carbon-containing hard mask, and using the patterned metal-doped carbon-containing hard mask to etch the carbon material such that the use of a silicon-containing mask during etch of the carbon material is eliminated.

In some embodiments, a semiconductor structure can include: a diamond substrate having a surface conductive layer; a heavily doped region formed in the diamond substrate; and a metal contact positioned over the conductive surface layer such that a first portion of the heavily doped region is covered by the metal contact and a second portion of the heavily doped region is not covered by the metal contact.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Provided is a three-dimensional memory device including a substrate, first and second stacked structures and an etching stop layer. The substrate has a cell region and a periphery region. The first stacked structure is disposed on the cell region and the periphery region, and has a first vertical channel pillar on the cell region that penetrates through the first stacked structure. The second stacked structure is located on the first stacked structure, is disposed on the cell region and the periphery region, and has a second vertical channel pillar on the cell region that penetrates through the second stacked structure. The second vertical channel pillar is electrically connected to the first vertical channel pillar. The etching stop layer is located between the first and second stacked structures, is disposed on the cell region and extends onto the periphery region, and surrounds the lower portion of the second vertical channel pillar.

A photosensitive composition of an embodiment includes: a resin containing at least one selected from polyacrylic acid, polymethacrylic acid, a cycloolefin-maleic anhydride copolymer, polycycloolefin, and a vinyl ether-maleic anhydride copolymer and having an ester bond which is caused to generate carboxylic acid by an acid or an ether bond which is caused to generate alcohol by an acid; and a photo acid generator which generates an acid by being irradiated with light, of which a wavelength is not less than 300 nm nor more than 500 nm, or KrF excimer laser light, the photo acid generator containing a substance that has a naphthalene ring or a benzene ring and in which at least one carbon atom of the naphthalene ring or the benzene ring is bonded to a bulky group.

An electrical device comprising a substrate of diamond material and elongate metal protrusions extending into respective recesses in the substrate. Doped semiconductor layers, arranged between respective protrusions and the substrate, behave as n type semiconducting material on application of an electric field, between the protrusions and the substrate, suitable to cause a regions of positive space charge within the semiconductor layers.

The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.