Methods are disclosed for forming a multi-layer structure including highly controlled diffusion interfaces between alternating layers of different semiconductor materials. According to embodiments, during a deposition of semiconductor layers, the process is controlled to remain at low temperatures such that an inter-diffusion rate between the materials of the deposited layers is managed to provide diffusion interfaces with abrupt Si/SiGe interfaces. The highly controlled interfaces and first and second layers provide a multi-layer structure with improved etching selectivity. In an embodiment, a gate all-around (GAA) transistor is formed with horizontal nanowires (NWs) from the multi-layer structure with improved etching selectivity. In embodiments, horizontal NWs of a GAA transistor may be formed with substantially the same size diameters and silicon germanium (SiGe) NWs may be formed with “all-in-one” silicon (Si) caps.

A method of forming a semiconductor device includes forming a trench in a semiconductor body; at least partially filling the trench with a filling material, the filling material; introducing dopants into a portion of the filling material, where the dopants have a first diffusion coefficient relative to the filling material and have a second diffusion coefficient relative to the semiconductor body, where the first diffusion coefficient is greater than the second diffusion coefficient, and where a ratio of the first diffusion coefficient to the second diffusion coefficient is greater than 10; and applying thermal processing to the semiconductor body configured to spread the dopants in the filling material along a vertical direction between a bottom side and a top side of the filling material by a diffusion process.

A method for thermally processing a substrate having a surface region and a buried region with a pulsed light beam, the substrate presenting an initial temperature-depth profile and the surface region presenting an initial surface temperature, including steps of: illuminating the surface region with a preliminary pulse so that it generates an amount of heat and reaches a predetermined preliminary surface temperature; and illuminating the surface region with a subsequent pulse after a time interval so that it reaches a predetermined subsequent surface temperature. The time interval is determined such that the surface region reaches a predetermined intermediate surface temperature greater than the initial surface temperature, such that during the time interval, the amount of heat is diffused within the substrate down to a predetermined depth so that the substrate presents a predetermined intermediate temperature-depth profile.

A method of forming a semiconductor device and a semiconductor device are provided. The method includes forming a graphene layer at a first side of a silicon carbide substrate having at least next to the first side a first defect density of at most 500/cm.sup.2. An acceptor layer is attached at the graphene layer to form a wafer-stack. The acceptor layer includes silicon carbide having a second defect density higher than first defect density. The wafer-stack is split along a split plane in the silicon carbide substrate to form a device wafer including the graphene layer and a silicon carbide split layer at the graphene layer. An epitaxial silicon carbide layer extending to an upper side of the device wafer is formed on the silicon carbide split layer. The device wafer is further processed at the upper side.

A p-type base region is configured by a p.sup.-type channel region and a p-type high-impurity-concentration region adjacent to the channel region in a horizontal direction. A point having a highest impurity concentration in the high-concentration region is located at a position separated from a lower surface of an n.sup.++-type source region. The impurity concentration in the high-impurity-concentration region decreases toward the front surface of the semiconductor substrate and the rear surface of the semiconductor substrate in the depth direction. The impurity concentration in the high-impurity-concentration region decreases toward the low-impurity-concentration region in a direction parallel to the front surface of the semiconductor substrate.

A semiconductor device includes a drift region, an active region in the drift region, and an edge termination region in the drift region adjacent to the active region. The edge termination region includes one or more guard rings in the drift region. The drift region has a first conductivity type and the one or more guard rings have a second conductivity type. The edge termination region may also include a passivation layer that is disposed on the one or more guard rings and on the drift region in the edge termination region. The passivation layer has a first thickness over each guard ring and a second thickness over the drift region, where the first thickness is greater than the second thickness. Alternatively, the edge termination region may also include a passivation layer that is only disposed on the one or more guard rings in the edge termination region.

A semiconductor device includes a silicon carbide body that includes a first section and a second section. The first section is adjacent to the second section. A drift region is formed in the first section and the second section. A lattice defect region is in a portion of the drift region in the second section. A first density of lattice defects, which include interstitials and vacancies in the lattice defect region, is at least double a second density of lattice defects, which include interstitials and vacancies in a portion of the drift region outside the lattice defect region.

An enhanced symmetric multicycle rapid thermal annealing process for removing defects and activating implanted dopant impurities in a III-nitride semiconductor sample. A sample is placed in an enclosure and heated to a temperature T.sub.1 under an applied pressure P.sub.1 for a time t.sub.1. While the heating of the sample is maintained, the sample is subjected to a series of rapid laser irradiations under an applied pressure P.sub.2 and a baseline temperature T.sub.2. Each of the laser irradiations heats the sample to a temperature T.sub.max above its thermodynamic stability limit. After a predetermined number of temperature pulses or a predetermined period of time, the laser irradiations are stopped and the sample is brought to a temperature T.sub.3 and held at T.sub.3 for a time t.sub.3 to complete the annealing.

What is proposed is a method of producing at least two differently heavily doped subzones (3, 5) predominantly doped with a first dopant type in a silicon substrate (1), in particular for a solar cell. The method comprises: covering at least a first subzone (3) of the silicon substrate (1) in which a heavier doping with the first dopant type is to be produced with a doping layer (7) of borosilicate glass, wherein at least a second subzone (5) of the silicon substrate (1) in which a lighter doping with the first dopant type is to be produced is not covered with the doping layer (7), and wherein boron as a dopant of a second dopant type differing from the first dopant type and oppositely polarized with respect to the same is included in the layer (7), and; heating the such prepared silicon substrate (1) to temperatures above 300 C., preferably above 900 C., in a furnace in an atmosphere containing significant quantities of the first dopant type. Additionally, at least a third doped subzone (15) doped with the second dopant type may be produced by the method additionally comprising, prior to the heating, a covering of the doping layer (7), above the third doped subzone (15) to be produced, with a further layer (17) acting as a diffusion barrier for the first dopant type. The method uses the observation that a borosilicate glass layer seems to promote an in-diffusion of phosphorus from a gas atmosphere and may substantially facilitate a manufacturing for example of solar cells, in particular back contact solar cells.

A semiconductor device and its manufacturing method, relating to semiconductor techniques. The semiconductor device manufacturing method comprises: forming a patterned first hard mask layer on a substrate to define a position for buried layers; conducting a first ion implantation using the first hard mask layer as a mask to form a first buried layer and a second buried layer both having a first conductive type and separated from each other at two sides of the first hard mask layer in the substrate; conducting a second ion implantation to form a separation region with a second conductive type opposite to the first conductive type in the substrate between the first and the second buried layers; removing the first hard mask layer; and forming a semiconductor layer on the substrate. This inventive concept reduces an area budget of a substrate and simplifies the manufacturing process.