Patent classifications
H01L21/12
Semiconductor devices including a support pattern on a lower electrode structure
Semiconductor devices are provided. A semiconductor device includes a first portion of a lower electrode structure on a substrate. The semiconductor device includes a first support pattern being in contact with a first portion of a sidewall of the first portion of the lower electrode structure. The semiconductor device includes a second portion of the lower electrode structure on a second portion of the sidewall of the first portion of the lower electrode structure. The semiconductor device includes an upper electrode on the second portion of the lower electrode structure and on the first support pattern. Moreover, the semiconductor device includes a dielectric layer between the upper electrode and the second portion of the lower electrode structure.
Critical methodology in vacuum chambers to determine gap and leveling between wafer and hardware components
Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.
Critical methodology in vacuum chambers to determine gap and leveling between wafer and hardware components
Implementations described herein generally relate to methods for leveling a component above a substrate. In one implementation, a test substrate is placed on a substrate support inside of a processing chamber. A component, such as a mask, is located above the substrate. The component is lowered to a position so that the component and the substrate are in contact. The component is then lifted and the particle distribution on the test substrate is reviewed. Based on the particle distribution, the component may be adjusted. A new test substrate is placed on the substrate support inside of the processing chamber, and the component is lowered to a position so that the component and the new test substrate are in contact. The particle distribution on the new test substrate is reviewed. The process may be repeated until a uniform particle distribution is shown on a test substrate.
Light emitting device and manufacturing method thereof, backlight module, display panel and display device
Provided are a light emitting device and manufacturing method thereof, a backlight module, a display panel and a display device. The manufacturing method includes: providing a substrate; forming a circuit layer on a side of the substrate; providing at least one switching element and at least one light emitting element; and electrically connecting the switching element and the light emitting element to the circuit layer. The circuit layer includes a first power signal line, a second power signal line, and a pulse width modulation signal line; the switching element includes a control terminal, a first terminal and a second terminal; the light emitting element is electrically connected between the first terminal and the first power signal line, or the light emitting element is electrically connected between the second terminal and the second power signal line.
SEMICONDUCTOR DEVICES INCLUDING A SUPPORT PATTERN ON A LOWER ELECTRODE STRUCTURE
A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.
SEMICONDUCTOR DEVICES INCLUDING A SUPPORT PATTERN ON A LOWER ELECTRODE STRUCTURE
A method of manufacturing a semiconductor device includes: forming electrode holes by etching a mold structure including a mold layer and a support layer which are stacked on a substrate; forming lower electrode pillars filling the electrode holes; etching a portion of the support layer between the lower electrode pillars to form a support pattern having a through-hole exposing a portion of a top surface of the mold layer; removing the mold layer through the through-hole to expose sidewalls of the lower electrode pillars; and selectively forming lower electrode patterns on the sidewalls and top surfaces of the lower electrode pillars.
TRANSFER DEVICE
A transfer device for transferring a plurality of micro LED dies is provided. The transfer device includes a carrier plate, a plurality of deformable components, and a plurality of transfer heads. The plurality of deformable components are disposed on the carrier plate. The plurality of transfer heads are respectively disposed on the plurality of deformable components. Each of the transfer heads includes a plurality of micro protrusions arranged in an array on a side away from the corresponding one deformable component. Deformation of the deformable components leads to deformation of the transfer heads, such that a number of the micro protrusions in contact with the micro LED dies is decreased. Accordingly, the transfer device can easily release the micro LED dies.
Methods for forming fins
The disclosure is directed to methods for forming a set of fins from a substrate. One embodiment of the disclosure includes: providing a stack over the substrate, the stack including a first oxide over the substrate, a first nitride over the pad oxide, a second oxide over the first nitride, and a first hardmask over the second oxide; patterning the first hard mask to form a first set of hardmask fins over the second oxide; oxidizing the first set of hardmask fins to convert the first set of hardmask fins into a set of oxide fins; using the set of oxide fins as a mask, etching the second oxide and the first nitride to expose portions of the first oxide thereunder such that remaining portions of the second oxide and the first nitride remain disposed beneath the set of oxide fins thereby defining a set of mask stacks; and using the set of mask stacks as a mask, etching the exposed portions of the first oxide and the substrate thereby forming the set of fins from the substrate.
Device and method used for measuring wafers
The present disclosure relates to a device and method for measuring wafers. The device comprises: a moving platform, which is used to adjust the location of wafers; a first pre-alignment module and a first image recognition module, which are used to align a first wafer at a first location on the moving platform before measuring the first wafer; a second pre-alignment module and a second image recognition module, which are used to align a second wafer at a second location on the moving platform before measuring the second wafer; and a measurement module, which is used to measure the first wafer and the second wafer at a third location on the moving platform, wherein the first location, second location and third location are different from each other. The embodiments of the present disclosure may improve the measurement efficiency of the device.
Touch panel, manufacturing method thereof and touch display device
The present disclosure provides a touch panel, a manufacturing method thereof and a touch display device. In one embodiment, the method comprises the following steps: 1) forming touch lines, comprising: forming in the same layer gate lines and a plurality of first touch lines, each first touch line being arranged intermittently in a direction of data lines and not electrically connected with the gate lines, and forming in the same layer a plurality of first connection lines and electrodes which are not in the same layer as the gate lines and the touch electrodes, each first connection line being used for connecting in series with an intermittent first touch line, each touch line comprising a first touch line and a plurality of first connection lines; and 2) forming touch electrodes, each touch electrode being electrically connected with one or more first touch lines, one or more is second touch lines, or one or more third touch lines. Accordingly, the manufacturing process steps of a self-capacitance in-cell touch panel can be reduced and the process can be simplified.