A method for assembling two substrates by molecular adhesion comprises: a first step (a) of putting first and second substrates in close contact in order to form an assembly having an assembly interface; a second step (b) of reinforcing the degree of adhesion of the assembly beyond a threshold adhesion value at which water is no longer able to diffuse along the assembly interface. The method also comprises a step (c) of anhydrous treatment of the first and second substrates in a treatment atmosphere having a dew point below −10° C., and control of the dew point of a working atmosphere to which the first and second substrates are exposed from the anhydrous treatment step (c) until the end of the second step (b) so as to limit or prevent the appearance of bonding defects at the assembly interface.

A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force F.sub.H1 and holding the second substrate to a second sample holder surface of a second sample holder with a holding force F.sub.H2; contacting the contact faces at a bond initiation point and heating at least the second sample holder surface to a heating temperature T.sub.H; bonding of the first substrate with the second substrate along a bonding wave running from the bond initiation point to the side edges of the substrates, wherein the heating temperature T.sub.H is reduced at the second sample holder surface during the bonding.

The invention relates to a method of joining substrates. It is the object of the invention in this respect to join substrates of substrate materials together without having to exert an increased effort for a coating with additional coating processes to be carried out and to be able to achieve a good quality of the join connection in so doing. In the method in accordance with the invention a pretreatment of at least one join surface of a substrate to be joined is carried out in low pressure oxygen plasma prior to the actual joining. On the joining, a contact force acts on the substrates to be joined in the range 2 kPa to 5 MPa and in this process a heat treatment is carried out at an elevated temperature of at least 100° C. and at under pressure conditions of a maximum of 10 mbar, preferably <10.sup.−3 mbar.

Provided herein are methods of selectively etching silicon-containing block copolymer (BCP) materials. The methods involve exposing a BCP material that includes at least one silicon-containing block and at least one non-silicon-containing block to a plasma that has a reducing chemistry. The reducing plasma selectively removes the non-silicon-containing block, the silicon-containing block to be used in further processing. In some embodiments, the silicon-containing block is used as an etch mask. The reducing plasma reduces or eliminates profile bowing and undercut of the silicon-containing domains, allowing processing of high aspect ratio features. Examples of reducing chemistries include nitrogen (N.sub.2), hydrogen (H.sub.2), ammonia (NH.sub.3), hydrazine (N.sub.2H.sub.4), and mixtures thereof. Also provided are apparatuses to perform the methods.

In one embodiment of the present invention, a resistive switching device includes a first electrode disposed over a substrate and coupled to a first potential node, a switching layer disposed over the first electrode, a conductive amorphous layer disposed over the switching layer, and a second electrode disposed on the conductive amorphous layer and coupled to a second potential node.

The invention relates to an avalanche diode that can be employed as an ESD protection device. An avalanche ignition region is formed at the p-n junction of the diode and includes an enhanced defect concentration level to provide rapid onset of avalanche current. The avalanche ignition region is preferably formed wider than the diode depletion zone, and is preferably created by placement, preferably by ion implantation, of an atomic specie different from that of the principal device structure. The doping concentration of the placed atomic specie should be sufficiently high to ensure substantially immediate onset of avalanche current when the diode breakdown voltage is exceeded. The new atomic specie preferably comprises argon or nitrogen, but other atomic species can be employed. However, other means of increasing a defect concentration level in the diode depletion zone, such as an altered annealing program, are also contemplated.

The present disclosure relates to a method for reducing metal contamination on a surface of a substrate. The method involves plasma treatment of the surface of the substrate by ion bombardment, wherein a plasma of a supplied gas is generated, and a bombardment energy of the ions in the plasma is controlled by a radio frequency electromagnetic field. The bombardment energy of the ions is higher than a first threshold so as to tear the metal contamination from the surface of the substrate, and the bombardment energy of the ions is lower than a second threshold so as to prevent a surface quality degradation of the surface of the substrate.

A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

A method includes performing an anneal on a wafer. The wafer includes a wafer-edge region, and an inner region encircled by the wafer-edge region. During the anneal, a first power applied on a portion of the wafer-edge region is at least lower than a second power for annealing the inner region.

The inventive concepts provide semiconductor devices and methods of fabricating the same. According to the method, sub-stack structures having a predetermined height and active holes are repeatedly stacked. Thus, cell dispersion may be improved, and various errors such as a not-open error caused in an etching process may be prevented. A grain size of an active pillar used as channels may be increased or maximized using a metal induced lateral crystallization method, so that a cell current may be improved. A formation position of a metal silicide layer including a crystallization inducing metal may be controlled such that a concentration grade of the crystallization inducing metal may be controlled depending on a position within the active pillar.