Systems and methods for gallium nitride growth on silicon. A semiconductor device, comprising a silicon (001) substrate. A graphene layer on the silicon (001) substrate, wherein the graphene layer is synthesized without a metallic catalyst, and a gallium nitride-based layer over the graphene layer. Methods for growing a gallium nitride layer on silicon are also taught.

An apparatus including a carrier substrate configured to move a microelectronic device. The apparatus further includes a rotatable body configured to receive the microelectronic device. Additionally, the apparatus includes a second substrate configured to receive the microelectronic device from the rotatable body.

A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without forming an oxide layer at the bonded interface also for the substrate having surface that is hardly planarized. The manufacturing method for the semiconductor substrate may include an amorphous layer formation process in which a first amorphous layer is formed by modifying a surface of a support substrate and a second amorphous layer is formed by modifying a surface of a single-crystalline layer of a semiconductor. The manufacturing method may include a contact process in which the first amorphous layer and the second amorphous layer are contacted with each other. The manufacturing method may include a heat treatment process in which the support substrate and single-crystalline layer are heat-treated with the first amorphous layer and the second amorphous layer being in contact with each other.

The disclosed technology relates generally to a method and system for micro assembling GaN materials and devices to form displays and lighting components that use arrays of small LEDs and high-power, high-voltage, and or high frequency transistors and diodes. GaN materials and devices can be formed from epitaxy on sapphire, silicon carbide, gallium nitride, aluminum nitride, or silicon substrates. The disclosed technology provides systems and methods for preparing GaN materials and devices at least partially formed on several of those native substrates for micro assembly.

A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit lines being separate from the substrate with an insulating layer therebetween; a plurality of first insulating lines extending in a second direction that is different from the first direction, wherein the plurality of first insulating lines intersect the plurality of bit lines and have upper surfaces having levels which are higher than those of upper surfaces of the plurality of bit lines relative to the substrate; and a plurality of first contact structures connected to the plurality of active regions, the plurality of first contact structures being disposed in an area defined by the plurality of bit lines and the plurality of first insulating lines.

A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.

In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less. The structure has a first bonding medium provided between the first handle substrate and each of the substrate while maintaining the alignment between reference crystal orientation and the selected direction of the first handle substrate; and a processed region formed overlying each of the substrates configured concurrently while being bonded to the first handle substrate. Depending upon the embodiment, the processed region can include any combination of the aforementioned processing steps and/or steps.

Stacked planar capacitor structures and methods of fabricating the same generally include stacking two or more capacitors with three electrodes by sharing a middle electrode, wherein each capacitor has a different area. The stacked structure does not include step heights, which permits fabrication of multiple structures where desired.

A method includes placing a wafer into a production chamber, providing a heating source to heat the wafer, and projecting a laser beam on the wafer using a laser projector. The method further includes, when the wafer is heated by both of the heating source and the laser beam, performing a process selected from an epitaxy process to grow a semiconductor layer on the wafer, and an etching process to etch the semiconductor layer.

A method includes placing a wafer into a production chamber, providing a heating source to heat the wafer, and projecting a laser beam on the wafer using a laser projector. The method further includes, when the wafer is heated by both of the heating source and the laser beam, performing a process selected from an epitaxy process to grow a semiconductor layer on the wafer, and an etching process to etch the semiconductor layer.