Stacked planar capacitors with scaled EOT

Abstract

Stacked planar capacitor structures and methods of fabricating the same generally include stacking two or more capacitors with three electrodes by sharing a middle electrode, wherein each capacitor has a different area. The stacked structure does not include step heights, which permits fabrication of multiple structures where desired.

Claims

1. A method of forming a stacked planar capacitor at BEOL, comprising: providing a substrate including a first dielectric layer; forming a first electrode and a first isolation region on the first dielectric layer, wherein the first electrode has a thickness equal to the first isolation region; forming a first high-k dielectric material layer on the first electrode and the first isolation region layer; forming a second electrode and a second isolation region on the first high dielectric layer, wherein the second electrode has a thickness equal to the second isolation region; forming a second high-k dielectric material layer on the second electrode and the second isolation region, wherein the second electrode overlays a portion of the first electrode; forming a third electrode on the second high dielectric layer, wherein the third electrode has a thickness equal to a thickness of the second isolation region, and wherein the third electrode has a width equal to the first electrode and is vertically aligned therewith; forming a second dielectric layer on the third electrode and an exposed portion of the second high k dielectric layer; forming a first vertical via to the first and third electrodes; forming a second vertical via to the second electrode; and filling the first and second vertical vias with a conductive material to form the stacked planar capacitor.

2. The method of claim 1, wherein forming the first and second vertical via is simultaneous.

3. The method of claim 1, wherein the first vertical via stops at the first electrode, and the second vertical via stops at the second electrode.

4. The method of claim 1, wherein forming the first high-k dielectric material layer comprises patterning the first high k dielectric layer to have a width equal to the second electrode, wherein the second electrode is vertically aligned therewith, and wherein the second isolation region is at a thickness equal to a combined thickness of the second electrode and the high k dielectric layer such that the second isolation region has a top surface coplanar to a top surface of the second electrode.

5. The method of claim 4, further comprising patterning the second high k dielectric layer to have a width equal to the third electrode during the forming of the second high-k dielectric material layer, wherein the third electrode is vertically aligned therewith.

6. The method of claim 5, wherein the first vertical via stops at the first electrode, and the second vertical via stops at the second electrode.

7. The method of claim 1, wherein the first and second high k dielectric layers comprise oxide-nitride-oxide, SiO.sub.2, Ta.sub.2O.sub.5, Si.sub.3N.sub.4, SiON, ZrO.sub.2, HfO.sub.2, HfSiO.sub.2, Al.sub.2O.sub.3, and any combination of two or more of the foregoing materials.

8. The method of claim 1, wherein the first, second, and third electrodes comprise titanium nitride.

9. The method of claim 1, wherein said first high-k dielectric material layer and said second high-k dielectric material layer are formed from the same dielectric material, said dielectric material comprises oxide-nitride-oxide, SiO.sub.2, Ta.sub.2O.sub.5, Si.sub.3N.sub.4, SiON, ZrO.sub.2, HfO.sub.2, Al.sub.2O.sub.3, or any combination of two or more of the foregoing materials.

10. The method of claim 1, wherein said forming the first and second high-k dielectric material layers comprises a chemical vapor deposition (CVD), a plasma enhanced chemical vapor deposition (PECVD), an atomic layer deposition (ALD) process, or a plasma enhanced atomic layer deposition (PEALD).

11. The method of claim 1, wherein the first, second, and third electrodes comprise Ta, Ru, Co, Pt, W, Rh, Ir, Au, Al, Ti, nitrides thereof or an alloy of two or more of the foregoing materials.

12. The method of claim 1, further comprising forming a third isolation region on the second high dielectric layer, wherein the third electrode has a thickness equal to the third isolation region; forming at least one additional high-k dielectric material layer on the third electrode and the third isolation region; forming at least one additional electrode and at least one additional isolation region on the third high k dielectric layer, wherein the at least one additional electrode has a thickness equal to the at least one additional isolation region; wherein the at least one additional electrode overlays at least a portion of the third electrode, and wherein the at least one additional electrode has a width equal to the second electrode and is vertically aligned therewith.

13. The method of claim 1, wherein filling the first and second vertical vias with the conductive material comprises depositing Cu, Al, W, Ru, Rh, Ir, Co, or an alloy comprising two or more of the foregoing metals.

14. The method of claim 1, wherein forming the first electrode and the first isolation region on the first dielectric layer comprises patterning the first electrode on the first dielectric layer; depositing a layer of a material defining the isolation region onto the patterned first electrode, wherein the layer of the material defining the isolation region is at a thickness greater than a thickness of the first electrode; and polishing the layer such that the thickness of the isolation region is equal to the thickness of the first electrode.

15. A stacked planar capacitor structure comprising at least two capacitors, the stacked planar capacitor structure comprising: a first capacitor formed on an interlevel or an intralevel dielectric of BEOL comprising a first layer defined by a first bottom electrode and a first isolation region, wherein the first electrode and the first isolation region are of equal thickness; a second layer defined by a middle electrode and a second isolation region, wherein the middle electrode and the second isolation region are of equal thickness, and wherein the middle electrode overlays a portion of the first bottom electrode; and a first high k dielectric layer intermediate the first and second layers; and a second capacitor comprising a third layer defined by a second bottom electrode; the second layer defined by the middle electrode and the second isolation region; and a high k dielectric layer intermediate the third layer and the second layer; wherein the first and second bottom electrodes and the middle electrode are stackedly arranged vertically, wherein the first and second bottom electrodes have the same width and are vertically aligned with each other, and wherein the first and second capacitors share the middle electrode.

16. The stacked planar capacitor structure of claim 15, further comprising a first vertical metal contact between at least the first bottom electrode and the second bottom electrode; and a second vertical metal contact to the middle electrode.

17. The stacked planar capacitor structure of claim 15, wherein the first and second high k dielectric layers comprise oxide-nitride-oxide, SiO.sub.2, Ta.sub.2O.sub.5, Si.sub.3N.sub.4, SiON, ZrO.sub.2, HfO.sub.2, HfSiO.sub.2, Al.sub.2O.sub.3, and any combination of two or more of the foregoing materials.

18. A stacked planar capacitor structure comprising at least two capacitors, the stacked planar capacitor structure comprising: a first capacitor formed on an interlevel or an intralevel dielectric of BEOL comprising: a first layer defined by a first bottom electrode and a first isolation region, wherein the first electrode and the first isolation region are of equal thickness; a first high k dielectric layer offset from and overlaying a portion of the first bottom electrode; a middle electrode vertically aligned with and of an equal width as the first high k dielectric layer; and a second isolation region abutting the middle electrode having a thickness equal to the middle electrode and the first high k dielectric layer such that the second isolation region has an upper surface coplanar with the middle electrode; and a second capacitor comprising: a third layer defined by a second bottom electrode; the middle electrode; and a second high k dielectric layer intermediate the third layer and the middle electrode; the second high k dielectric layer offset from and overlaying a portion of the middle electrode, wherein the second bottom electrode is vertically aligned with and of an equal width as the second high k dielectric layer and the first bottom electrode, wherein the first and second capacitors share the middle electrode.

19. The stacked planar capacitor structure of claim 15, further comprising a first vertical metal contact between at least the first bottom electrode and the second bottom electrode; and a second vertical metal contact to the middle electrode.

20. The stacked planar capacitor structure of claim 15, wherein the first and second high k dielectric layers comprise oxide-nitride-oxide, SiO.sub.2, Ta.sub.2O.sub.5, Si.sub.3N.sub.4, SiON, ZrO.sub.2, HfO.sub.2, HfSiO.sub.2, Al.sub.2O.sub.3, and any combination of two or more of the foregoing materials.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

(2) Prior Art FIG. 1 is a transmission electron micrograph of a semiconductor device including a via extending between metal levels and a prior art stacked MIM decoupling capacitor;

(3) Prior Art FIG. 2 is a transmission electron micrograph of a magnified view of the stacked MIM decoupling capacitor of the semiconductor device of prior art FIG. 1;

(4) FIG. 3 illustrates a cross-sectional view of 3D via stacked planar capacitors after an initial processing stage, in accordance with embodiments of the present invention;

(5) FIG. 4 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(6) FIG. 5 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(7) FIG. 6 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(8) FIG. 7 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(9) FIG. 8 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(10) FIG. 9 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(11) FIG. 10 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(12) FIG. 11 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(13) FIG. 12 illustrates a cross-sectional view of 3D via stacked planar capacitors after another processing stage, in accordance with embodiments of the present invention;

(14) FIG. 13 is a cross-sectional view of an array of two 3D via stacked planar capacitors formed by the processing stages of FIGS. 3-12, in accordance with one or more embodiments of the present invention:

(15) FIG. 14 is a cross-sectional view of an array of two 3D via stacked planar capacitors, in accordance with an embodiment of the present invention;

(16) FIG. 15 is a cross-sectional view of an array of two 3D via stacked planar capacitors, in accordance with an embodiment of the present invention; and

(17) FIG. 16 is a cross-sectional view of an array of two 3D via stacked planar capacitors, in accordance with an embodiment of the present invention.

(18) It will be appreciated that for simplicity and clarity of illustration, elements shown in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for purpose of clarity.

DETAILED DESCRIPTION

(19) The present invention will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the illustrated embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numerals refer to like features throughout.

(20) It will be understood that when an element, such as a layer, is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present.

(21) Disclosed herein are methods and structures for forming one or more stacked planar electrode capacitors with scaled equivalent oxide thickness (EOT). The methods and structures overcome the problems associated in the prior art by eliminating step heights for the dielectric layer so as to enable aggressive EOT scaling. The stacked planar configuration in accordance with the present invention as will be discussed below eliminates weak spots observed with stacked capacitors including non-planar dielectrics. In the present disclosure, the high k dielectric layer between electrodes can further function as an etch stop layer for subsequent planar electrode/isolation layer deposition. As will be apparent to those skilled in the art, the fabrication methods and stacked planar capacitor structures enables stacking of three or more electrodes, thereby providing capacitance enhancement. Multiple repetition of the structure is possible without causing additional topography, which is a significant advantage over the prior art.

(22) Referring now to FIG. 3, a structure 100 is provided, which includes formation of the first bottom electrode (BE1). The structure 100 includes a dielectric layer 102 including a planar top surface. The dielectric layer 102 may be any interlevel or intralevel dielectrics utilized at the back end of line (BEOL). As used herein, BEOL generally begins when the first layer of metal is deposited on the wafer. As such, BEOL typically includes contacts, insulating layers, metal levels, and bonding sites for chip-to-package connections. The dielectric layers used in the BEOL may include inorganic dielectrics or organic dielectrics and the planar capacitor structure and method of formation can advantageously be inserted at any level of the BEOL.

(23) The dielectric layer 102 may be porous or non-porous. Examples of suitable dielectrics that can be used as the dielectric layer 102 include, but are not limited to, SiO.sub.2, silsesquioxanes, C doped oxides (i.e., organosilicates) that include atoms of Si, C, O and H, thermosetting polyarylene ethers, or multilayers thereof. The term “polyarylene” is used in this application to denote aryl moieties or substituted aryl moieties which are linked together by bonds, fused rings, or inert linking groups such as, for example, oxygen, sulfur, sulfone, sulfoxide, carbonyl and the like.

(24) In one or more embodiments, the dielectric layer 102 has a dielectric constant of about 4.0 or less. In other embodiments, the dielectric layer 102 has a dielectric constant of about 2.8 or less. These dielectrics generally have a lower parasitic crosstalk as compared with dielectric materials that have a dielectric constant higher than 4.0. The dielectric constants mentioned herein are measured in a vacuum.

(25) A first bottom electrode 104 (also shown as BE1) is formed on the top surface of the dielectric layer 102. In one or more embodiments, the first bottom electrode 104 is a conductive material. Conductive materials suitable for the first electrode of the capacitor structure include, but are not limited to, Ta, Ru, Co, Pt, W, Rh, Ir, Au, Al, Ti, nitrides thereof, and an alloy of two or more of the foregoing materials. In one or more embodiments, the first electrode is TiN. The first bottom electrode 104 may be formed by first depositing a layer of the first electrode material utilizing a conventional deposition process such as, for example, PVD, CVD, PECVD, an atomic layer deposition (ALD) process, or a plasma enhanced atomic layer deposition (PEALD). Typically, the first electrode has a thickness from about 5 nm to about 100 nm, with a thickness from about 20 nm to about 40 nm being more typical.

(26) A layer of the first electrode material can be patterned by a lithographic process to form the first bottom electrode 104. For example, a photoresist (not shown) can be formed atop the first electrode layer by a conventional deposition process such as, for example, spin-on coating or chemical solution deposition. The photoresist may be a positive-tone or a negative-tone photoresist. The photoresist is then subjected to a lithographic process which includes exposing the photoresist to a pattern of radiation and developing the exposed resist utilizing a conventional resist developer. The lithographic step provides a patterned photoresist atop the layer of first electrode material that will be used to define the width of the first electrode 104. The pattern is transferred into the first electrode layer utilizing one or more etching processes to form the first electrode 104.

(27) The patterned photoresist can be stripped immediately after the electrode pattern is transferred by utilizing a conventional stripping and/or plasma ashing process. The etching used in transferring the electrode pattern may comprise a dry etching process, a wet chemical etching process or a combination thereof. The term “dry etching” is used herein to denote an etching technique such as reactive-ion etching, ion beam etching, plasma etching, or laser ablation.

(28) In FIG. 4, a layer of first isolation material 106 is then deposited onto the structure 100 at a thickness greater than the thickness of the first electrode 104. In FIG. 5, the layer of first isolation material 106 is polished such as by chemical mechanical polishing (CMP) to provide first isolation regions 106 having a thickness equal to the first electrode 104 so as to form a flat surface. That is, the first electrode 104 has a top surface that is coplanar with the top surface of the isolation region 106. The isolation material defining the isolation region 106 can be a dielectric material such as, for example, an oxide such as SiO.sub.2 to a nitride such as Si.sub.3N.sub.4. The isolation layer can be formed utilizing a conventional deposition process such as, for example, CVD, PECVD, chemical solution deposition or evaporation. The thickness of the as-deposited isolation layer 106 may vary depending upon the type of isolation material formed and the deposition technique used in forming the same. By way of example, the as-deposited isolation layer has a thickness prior to CMP from about 15 nm to about 300 nm, with a thickness from about 60 nm to about 120 nm being more typical.

(29) The CMP process generally includes polishing the isolation layer stopping at the first electrode 104. CMP is a planarization process for smoothing surfaces with the combination of chemical and mechanical forces. The process generally includes an abrasive and corrosive chemical slurry (commonly a colloid) in conjunction with a polishing pad and retaining ring, typically of a greater diameter than the wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring. The dynamic polishing head is rotated with different axes of rotation. This removes excess isolation material and tends to even out any irregular topography, making the wafer flat or planar. The particular CMP process is not intended to be limited and will generally depend on the materials used to define the first electrode 104 and first isolation region 106. As will be discussed in greater detail below, the first electrode 104 and first isolation regions 106 will be configured as the first bottom electrode (BE1) in the capacitor structure of the present invention.

(30) Optionally, the isolation region 106 may be formed prior to forming the first bottom electrode 104. In this optional embodiment, a layer defining the isolation region would be deposited and lithographically patterned. The first electrode 104 would be deposited at a thickness about equal to the isolation region 106. The resulting structure may be polished to provide a co-planar surface to the first bottom electrode 104 and the isolation region 106 as well as to remove any excess tungsten.

(31) In FIG. 6, a first high-k dielectric material layer 108 is then formed on the layer defined by the first electrode 104 and the first isolation region 106. Materials suitable for the first high-k dielectric layer include, but are not limited to, oxide-nitride-oxide, SiO.sub.2, Ta.sub.2O.sub.5, Si.sub.3N.sub.4, SiON, ZrO.sub.2, ZrAlO, ZrSiO, HfAlO, HfO.sub.2, HfSiO.sub.2, Al.sub.2O.sub.3, and any combination of two or more of the foregoing materials. In one or more embodiments, the first high-k dielectric material layer has a dielectric constant of about 5 to about 60. In other embodiments, the first high-k dielectric material layer has a dielectric constant of about 8 to about 40. The dielectric constants mentioned herein are measured in a vacuum. The first high-k dielectric material layer may be formed utilizing a conventional deposition process such as, for example, CVD, PECVD, ALD, or PEALD. Because the underlying first electrode 104 and isolation region 106 have coplanar top surfaces without any stepped heights, the first high-k dielectric material layer 108 can have an aggressive EOT scaling. In one or more embodiments, the first high k dielectric layer 108 thickness is from about 2 nm to about 8 nm, with a thickness from about 4 nm to about 6 nm being more typical.

(32) In FIG. 7, a second electrode 110 is formed in the same manner as the first bottom electrode 104 discussed previously herein. In FIG. 8, a second isolation region 112 is formed in the same manner as the first isolation region 106 discussed above. More specifically, a layer of the second electrode material is deposited onto the high k dielectric layer 108 and patterned as described above. The second electrode material can be the same material or a different material used to define the first electrode 104. A portion of the second electrode 110 layer overlays the first electrode 104 and will be configured as the top (middle) electrode (TE) in the capacitor structure 100. As shown, the portion of the second electrode 110 overlays the one side of the cross sectional view of the first bottom electrode 104.

(33) As shown in FIG. 8, a layer of second isolation material is then deposited at a thickness greater than the second electrode 110 onto the structure 100. As shown in FIG. 9, the second isolation material is polished such as by chemical mechanical polishing (CMP) to provide second isolation region 112 having a thickness equal to the second electrode so as to form a flat surface. That is, the second electrode 110 has a top surface that is coplanar with the top surface of the second isolation region 112. The isolation material can be a dielectric material such as, for example, an oxide such as SiO.sub.2 to a nitride such as Si.sub.3N.sub.4. The second isolation material can be the same material or a different material used to define the first isolation region 106. The isolation layer can be formed utilizing a conventional deposition process such as, for example, CVD, PECVD, chemical solution deposition or evaporation. The thickness of the as-deposited isolation layer may vary depending upon the type of isolation material formed and the deposition technique used in forming the same. By way of example, the as-deposited isolation layer has a thickness from about 15 nm to about 300 nm, with a thickness from about 60 nm to about 120 nm being more typical.

(34) The CMP process generally includes polishing the isolation layer stopping at the second electrode 110.

(35) Optionally, the isolation region 112 may be formed prior to forming the second bottom electrode 110. In this optional embodiment, a layer defining the isolation region 112 would be deposited and lithographically patterned. The second bottom electrode 110 would then be deposited at a thickness about equal to the isolation region 112. The resulting structure may be polished to provide a co-planar surface to the second bottom electrode 110 and the isolation region 112 as well as to remove any excess tungsten.

(36) In FIG. 10, a second high-k dielectric material layer 114 is then formed over the planar surface of the second electrode 110 and second isolation region 112. Materials suitable for the second high-k dielectric layer include, but are not limited to, oxide-nitride-oxide, SiO.sub.2, Ta.sub.2O.sub.5, Si.sub.3N.sub.4, SiON, ZrO.sub.2, HfO.sub.2, HfSiO.sub.2, Al.sub.2O.sub.3, and any combination of two or more of the foregoing materials. The second high-k dielectric material layer 114 can be the same material or a different material as the first high-k dielectric material layer 108. In one or more embodiments, the second high-k dielectric material layer has a dielectric constant of about 5 to about 60. In other embodiments, the first high-k dielectric material layer has a dielectric constant of about 8 to about 40. The first high-k dielectric material layer may be formed utilizing a conventional deposition process such as, for example, CVD, PECVD, ALD, or PEALD. In one or more embodiments, the second high k dielectric layer 114 has a thickness from about 2 nm to about 8 nm, with a thickness from about 4 nm to about 6 nm being more typical. In one or more embodiments, the thickness of the second dielectric layer 114 is the same as the first high k dielectric layer 108.

(37) In FIG. 11, a third electrode 116 (which will function as the second bottom electrode (BE2)) is formed on the second high k dielectric layer 114. A layer of the third electrode material is deposited onto the third high k dielectric layer 114 and patterned as described above. The third electrode material can be the same material or a different material used to define the first and second electrodes 104, 110, respectively. The third electrode 116 has the same width as the first electrode 104 and is aligned therewith. As will be discussed in greater detail below, the third electrode 116 will be configured as the second bottom electrode (BE2) in the capacitor structure.

(38) In FIG. 12, dielectric layer 120 is deposited onto the structure 100. The dielectric layer 120 is similar to or the same as dielectric layer 102 and may be any one of the interlevel or intralevel dielectrics typically utilized at the back end of line (BEOL).

(39) In FIG. 13, via contact formation is shown, which uses one or hardmasks to penetrate all of the underlying layers as shown or to separately make contact to the bottommost BE and TE. As such, the vias generally extend from the top of dielectric layer 120 down to the metal lines. To form the vias 122, a patterned hardmask layer (not shown) is first formed atop the upper surface of the dielectric layer 120, e.g., the ILD. The hardmask layer can include an oxide, nitride, oxynitride, or a combination of two or more of the foregoing materials. In some embodiments, the hardmask layer may have a single layer or multilayer structure. In one or more embodiments, the hardmask layer is an oxide such as SiO.sub.2 or a nitride such as Si.sub.3N.sub.4. The hardmask layer can be formed utilizing a conventional deposition process such as, for example, CVD, PECVD, chemical solution deposition or evaporation. The thickness of the as-deposited hardmask layer may vary depending upon the type of hardmask material formed, the number of layers that make up the hardmask layer, the deposition technique used in forming the same, as well as the via formation process. Typically, the as-deposited hardmask layer has a thickness from about 10 nm to about 80 nm, with a thickness from about 20 nm to about 60 nm being more typical.

(40) The hardmask layer can be patterned by a lithographic process. A photoresist (not shown) is formed atop the hardmask layer by a conventional deposition process such as, for example, spin-on coating or chemical solution deposition. The photoresist may be a positive-tone or a negative-tone photoresist. The photoresist is then subjected to a lithographic process which includes exposing the photoresist to a pattern of radiation and developing the exposed resist utilizing a conventional resist developer. The lithographic step provides a patterned photoresist atop the hardmask layer that defines the width of the via 122. The via pattern is transferred into the hardmask layer and then subsequently into the underlying layers utilizing one or more etching processes.

(41) The patterned photoresist can be stripped immediately after the via pattern is transferred into the hardmask layer by utilizing a conventional stripping and/or plasma ashing process. The etching used in transferring the via pattern into the various layers, e.g., layers 102, 104, 108, 112, 114, 116, 120 for contact formation with the bottom electrodes (BE1, BE2), and layers 102, 106, 108, 110, 114, 120 for contact formation with the top electrode (TE). The etching process may comprise a dry etching process, a wet chemical etching process or a combination thereof. The term “dry etching” is used herein to denote an etching technique such as reactive-ion etching, ion beam etching, plasma etching, or laser ablation.

(42) The vias 122 are filled with a conductive metal. Typically, a tungsten layer is deposited into the via 122 using a chemical vapor deposition process or physical vapor deposition sputtering process. Then, either a metal chemical mechanical polishing (CMP) or an etch back technique is used to remove any tungsten lying outside the vias.

(43) Structure 100 in FIG. 13 advantageously utilizes 4 mask levels to form the 2 parallel capacitors as shown. It should be apparent that additional capacitors can be easily fabricated by repeating the formation of the bottom top electrodes; the entire structure of which can be inserted at any level of BEOL. In the embodiment shown, the mask levels are utilized for BE1, TE, BE2, and via formation. The vias penetrate through the stacks to make contacts to all bottom electrodes and top electrode(s) separately.

(44) FIG. 14 illustrates a stacked planar capacitor structure 200 in accordance with another embodiment. In this embodiment, the high k dielectric layers 108 and 114 are patterned prior to subsequent processing. High k dielectric layer 108 is patterned to provide a width equal to a width of the top electrode 110 (TE) so that the edges thereof are aligned and high k dielectric layer 114 is patterned to provide a width equal to the second bottom electrode 116 (BE2) so that the edges thereof are aligned. As in the previous embodiments, the isolation region 112 is made to be coplanar with the top electrode 110 so that the thickness of the isolation region 112 is equal to the combined thickness of the high k dielectric layer 108 and the top electrode 110. Vias 122 are formed in the same manner as capacitor structure 100 above. However, for contact formation with the bottom electrodes (BE1, BE2), the via 122 extends through layers 102, 104, 112, 114, 116, and 120, i.e., there is no high k dielectric layer 112 in the contact formation with the bottom electrodes (BE1, BE2).

(45) FIG. 15 illustrates a stacked planar capacitor structure 300 in accordance with another embodiment. In this embodiment, the vias 130, 140 are formed in the same manner as that described above but are selectively stopped at the bottom most bottom electrode 104 (BE1) and top electrode 110 (TE) to make separate contacts. As a result, an additional mask level is utilized to form the separate vias. The mask levels include BE1, TE, BE2, BE via formation and TE via formation.

(46) FIG. 16 illustrates a stacked planar capacitor structure 400 in accordance with another embodiment. In this embodiment, the high k dielectric layers 108 and 114 are patterned prior to subsequent processing. High k dielectric layer 108 is patterned to provide a width equal to a width of the top electrode 110 (TE) so that the edges thereof are aligned and high k dielectric layer 114 is patterned to provide a width equal to the second bottom electrode 116 (BE2) so that the edges thereof are aligned. In addition, the vias 150, 160 are selectively stopped at the bottom most bottom electrode 104 (BE1) and top electrode 110 (TE), respectively, to make separate contacts therewith. As a result, an additional mask level is utilized to form the separate vias. The mask levels include BEJ, TE, BE2, BE via formation and TE via formation.

(47) As described, the stacked planar capacitor structure includes at least two capacitors that share a middle electrode, i.e., top electrode 110, which results in each capacitor being in a different area. The stacked planar capacitor structures generally includes a first capacitor formed on an interlevel or an intralevel dielectric of BEOL comprising a first layer defined by a first bottom electrode and a first isolation region, wherein the first electrode and the first isolation region are of equal thickness; a second layer defined by a middle electrode and a second isolation region, wherein the middle electrode and the second isolation region are of equal thickness, and wherein the middle electrode overlays a portion of the first bottom electrode, and a first high k dielectric layer intermediate the first and second layers. A second capacitor includes a third layer defined by a second bottom electrode, the second layer defined by the middle electrode and the second isolation region; and a high k dielectric layer intermediate the third layer and the second layer. Consequently, the first and second bottom electrodes, and the middle electrode are stackedly arranged vertically, wherein the first and second bottom electrodes have the same width and are vertically aligned with each other, and wherein the first and second capacitors share the middle electrode, which overlays a portion of the first and second bottom electrodes. Stacking of additional electrodes is feasible given that there is no step height utilized in the structure that would affect current leakage and provide reliability issues.

(48) Advantageously, the capacitor structures provide no high k dielectric corners that can lead to leakage and reliability issues. The capacitor structures can be integrated into the BEOL and are typically disposed in close proximity to the interconnects. In one or more embodiments, the capacitor structures are located close to the power and ground nodes (or whichever nodes are being decoupled) to reduce the parasitic inductance.

(49) While the present invention has been particularly shown and described with respect to preferred embodiments, it will be understood by those skilled in the art that the foregoing and other changes in forms and details may be made without departing from the spirit and scope of the invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated but fall within the scope of the appended claims.