Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

A method for bonding a first substrate with a second substrate at respective contact faces of the substrates with the following steps: holding the first substrate to a first sample holder surface of a first sample holder with a holding force F.sub.H1 and holding the second substrate to a second sample holder surface of a second sample holder with a holding force F.sub.H2; contacting the contact faces at a bond initiation point and heating at least the second sample holder surface to a heating temperature T.sub.H; bonding of the first substrate with the second substrate along a bonding wave running from the bond initiation point to the side edges of the substrates, wherein the heating temperature T.sub.H is reduced at the second sample holder surface during the bonding.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Described herein is a method of bonding and/or debonding substrates. In one embodiment, at least one of the surfaces of the substrates to be bonded is comprised of an oxide. In one embodiment, the surfaces of both substrates comprise an oxide. A wet etch may then be utilized to debond the substrates by etching away the layers that have been bonded. In one embodiment, a fusion bonding process is utilized to bond two substrates, at least one substrate having a silicon oxide surface. In one exemplary etch, a dilute hydrofluoric (DHF) etch is utilized to etch the bonded silicon oxide surface, allowing for two bonded substrates to be debonded. In another embodiment, the silicon oxide may be a low density silicon oxide. In one embodiment, both substrates may have a surface layer of the low density silicon oxide which may be fusion bonded together.

Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

An exemplary method includes forming a fuse structure and forming a first cathode connector and a second cathode connector over the fuse structure. The fuse structure includes an anode, a cathode, and a fuse link extending between and connecting the anode and the cathode. The fuse link has a width defined between a first edge and a second edge, which extend a length of the fuse link. The cathode includes a central region defined by a first longitudinal axis and a second longitudinal axis extending respectively from the first edge and the second edge. The first cathode connector and the second cathode connector are equidistant respectively to the fuse link, the first cathode connector does not intersect the first longitudinal axis, and the second cathode connector does not intersect the second longitudinal axis, such that the central region is free of the first cathode connector and the second cathode connector.

In a method for manufacturing a nitride semiconductor light-emitting element by splitting a semiconductor layer stacked substrate including a semiconductor layer stacked body with a plurality of waveguides extending along the Y-axis to fabricate a bar-shaped substrate, and splitting the bar-shaped substrate along a lengthwise split line to fabricate an individual element, the waveguide in the individual element has different widths at one end portion and the other end portion and the center line of the waveguide is located off the center of the individual element along the X-axis, and in the semiconductor layer stacked substrate including a first element forming region and a second element forming region which are adjacent to each other along the X-axis, two lengthwise split lines sandwiching the first element forming region and two lengthwise split lines sandwiching the second element forming region are misaligned along the X-axis.

In a method for manufacturing a nitride semiconductor light-emitting element by splitting a semiconductor layer stacked substrate including a semiconductor layer stacked body with a plurality of waveguides extending along the Y-axis to fabricate a bar-shaped substrate, and splitting the bar-shaped substrate along a lengthwise split line to fabricate an individual element, the waveguide in the individual element has different widths at one end portion and the other end portion and the center line of the waveguide is located off the center of the individual element along the X-axis, and in the semiconductor layer stacked substrate including a first element forming region and a second element forming region which are adjacent to each other along the X-axis, two lengthwise split lines sandwiching the first element forming region and two lengthwise split lines sandwiching the second element forming region are misaligned along the X-axis.

A first raw material solution containing at least aluminum is atomized to generate first atomized droplets and a second raw material solution containing at least gallium and a dopant is atomized to generate second atomized droplets, and subsequently, the first atomized droplets are carried into a film forming chamber using a first carrier gas and the second atomized droplets are carried into the film forming chamber using a second carrier gas, and then the first atomized droplets and the second atomized droplets are mixed in the film forming chamber, and the mixed atomized droplets are thermally reacted in the vicinity of a surface of the base to form an oxide film on the base, the oxide film including, as a major component, a metal oxide containing at least aluminum and gallium, the oxide film having a corundum structure, wherein a principal surface of the oxide film is an m-plane.

A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.