A laser irradiation apparatus (1) according to an embodiment includes an optical-system module (20) configured to apply laser light (L1) to an object to be irradiated, a shield plate (51) in which a slit (54) is formed, through which the laser light (L1) passes, and a reflected-light receiving component (61) disposed between the optical-system module (20) and the shield plate (51), in which the reflected-light receiving component (61) is able to receive, out of the laser light (L1), reflected light (R1) reflected by the shield plate (51).

New temporary bonding methods and articles formed from those methods are provided. In one embodiment, the methods comprise coating a device or other ultrathin layer on a growth substrate with a rigid support layer and then bonding that stack to a carrier substrate. The growth substrate can then be removed and the ultrathin layer mounted on a final support. In another embodiment, the invention provides methods of handling device layers during processing that must occur on both sides of the fragile layer without damaging it. This is accomplished via the sequential use of two carriers, one on each side of the device layer, bonded with different bonding compositions for selective debonding.

A focus ring adjustment assembly of a system for processing workpieces under vacuum, where the focus ring may include a lower side having a first surface portion and a second surface portion, the first surface portion being vertically above the second surface portion. The adjustment assembly may include a pin configured to selectively contact the first surface portion of the focus ring, and an actuator operable to move the pin along the vertical direction between an extended position and a retracted position. The extended position of the pin may be associated with the distal end of the pin contacting the first surface of the focus ring and the focus ring being accessible for removal by a workpiece handling robot from the vacuum process chamber.

Resistor elements and methods of forming the resistor elements generally include increasing resistivity by diffusing nitrogen ions from an underlying dielectric layer into a metal resistor layer defining the resistor elements. One or more embodiments include a first resistor element and at least one additional resistor element disposed on a first dielectric material and at least one additional dielectric material, respectively, of a dielectric layer. The first dielectric material is different from the at least one additional dielectric material, and the first resistor element has a different resistivity than the at least one additional resistor element.

A vapor deposition apparatus includes an exhaust regulator provided in an exhaust pipe to regulate exhaust of the reaction chamber and including: a hollow frustum upstream baffle having a larger first opening near a reaction chamber than a second opening near an exhaust device; and a hollow frustum downstream baffle provided near the exhaust device with respect to the upstream baffle and having a larger third opening near the reaction chamber than a fourth opening near the exhaust device. The upstream baffle and downstream baffle are designed so that B/A and C/A are 0.33 or less, at least one of B/A and C/A is 0.26 or less, and (B+C)/A is 0.59 or less, where an inner diameter of the exhaust pipe and diameters of the first and third openings are A, a diameter of the second opening is B and a diameter of the fourth opening is C.

A vapor deposition apparatus includes an exhaust regulator provided in an exhaust pipe to regulate exhaust of the reaction chamber and including: a hollow frustum upstream baffle having a larger first opening near a reaction chamber than a second opening near an exhaust device; and a hollow frustum downstream baffle provided near the exhaust device with respect to the upstream baffle and having a larger third opening near the reaction chamber than a fourth opening near the exhaust device. The upstream baffle and downstream baffle are designed so that B/A and C/A are 0.33 or less, at least one of B/A and C/A is 0.26 or less, and (B+C)/A is 0.59 or less, where an inner diameter of the exhaust pipe and diameters of the first and third openings are A, a diameter of the second opening is B and a diameter of the fourth opening is C.

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.

A method and an apparatus for determining expansion compensation in a photoetching process, and a method for manufacturing a semiconductor device are provided. A relative vector misalignment value of a first wafer and a second wafer after being bonded is obtained based on a relative position relationship between a first alignment pattern of the first wafer and a second alignment pattern of the second wafer in a boding structure. A relative expansion value of the first wafer and the second wafer is obtained based on the relative vector misalignment value. A developing expansion compensation value in the photoetching process is obtained. The expansion compensation value is used to the photoetching process of a first conductor layer including the first alignment pattern of the first wafer and/or a second conductor layer including the second alignment pattern of the second wafer.

The stack capacitor structure includes a substrate, first, second, third, and fourth support layers, first, second, and third insulating layers, first, second, and third holes, and a capacitor. The first support layer is disposed over the substrate. The first insulating layer is disposed on the first support layer. The second support layer is disposed on the first insulating layer. The third support layer is disposed on the second support layer. The second insulating layer is disposed on the third support layer. The third insulating layer is disposed on the second insulating layer. The fourth support layer is disposed on the third insulating layer. The first hole penetrates through from the second support layer to the first support layer. The second and third holes penetrate through from the fourth support layer to the third support layer. The capacitor is disposed in the first, second, and third holes.