A semiconductor device includes a substrate: a first nitride semiconductor layer formed on the substrate; a second nitride semiconductor layer formed on the first nitride semiconductor layer and containing a gallium element; a source electrode and a drain electrode formed on the second nitride semiconductor layer and contacting the second nitride semiconductor layer; a third nitride semiconductor layer formed on the second nitride semiconductor layer and containing an indium element and an aluminum element; and a gate electrode formed on the third nitride semiconductor layer and formed between the source electrode and the drain electrode.

Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.

Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 110.sup.13 cm.sup.3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 110.sup.14 cm.sup.3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.

Some embodiments relate to a semiconductor device that includes a body region of a field effect transistor structure formed in a semiconductor substrate between a drift region of the field effect transistor structure and a source region of the field effect transistor structure. The semiconductor substrate includes chalcogen atoms at an atom concentration of less than 110.sup.13 cm.sup.3 at a p-n junction between the body region and the drift region, and at least part of the source region includes chalcogen atoms at an atom concentration of greater than 110.sup.14 cm.sup.3. Additional semiconductor device embodiments and corresponding methods of manufacture are described.

A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

Signal relay board for power semiconductor modules enabling electrical connection between power semiconductor modules and a drive unit driving same. A first wire layer, a second wire layer, a third wire layer, and a fourth wire layer of a multiphase wire portion are assigned with a first control wire layer serving as a path to provide a control signal to a first semiconductor device of the modules, a first ground wire layer serving as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the semiconductor modules, a second control wire layer serving as a path to provide a control signal to a second semiconductor device of the modules, and a second ground wire layer serving as a path to provide a ground potential to the second semiconductor device of the modules.

Signal relay board for power semiconductor modules enabling electrical connection between power semiconductor modules and a drive unit driving same. A first wire layer, a second wire layer, a third wire layer, and a fourth wire layer of a multiphase wire portion are assigned with a first control wire layer serving as a path to provide a control signal to a first semiconductor device of the modules, a first ground wire layer serving as a path to provide a ground potential to a low potential side terminal of the first semiconductor device of the semiconductor modules, a second control wire layer serving as a path to provide a control signal to a second semiconductor device of the modules, and a second ground wire layer serving as a path to provide a ground potential to the second semiconductor device of the modules.

A workpiece alignment system is provided has a light emission apparatus that directs a light beam at a plurality of wavelengths along a path at a shallow angle toward a first side of a workpiece plane at a peripheral region. A light receiver apparatus, receives the light beam on a second side opposite the first side. A rotation device selectively rotates a workpiece support. According controller determines a position of the workpiece based on an amount of the light beam received through the workpiece when the workpiece intersects the path. A sensitivity of the light receiver apparatus is controlled based on a transmissivity of the workpiece. A position of the workpiece is determined when the workpiece is rotated based on the rotational position, an amount of the light beam received, the transmissivity of the workpiece, detection of a workpiece edge, and the controlled sensitivity of the light receiver apparatus.

A semiconductor material layer is deposited on a p-type source/drain region of a p-type transistor device and an n-type source/drain region of an n-type transistor device. The p-type device transistor device and the n-type transistor device are formed on a substrate of a semiconductor device. The semiconductor device includes a trench formed through an inter-level dielectric layer. The inter-level dielectric layer is formed over the n-type transistor device and the p-type transistor device. The trench exposes the p-type source/drain region of the p-type transistor device and the n-type source/drain region of the n-type transistor device. An element is implanted in the semiconductor material layer to form an amorphous layer on p-type source drain region and the n-type source/drain region. The amorphous layer is annealed to form a first metastable alloy layer upon the p-type source/drain region and a second metastable alloy layer upon the n-type source/drain region.

A process of forming a HEMT that makes the contact resistance of a non-rectifying electrode consistent with other device performance is disclosed. The process includes steps of growing a GaN channel layer with a thickness smaller than 600 nm on a SiC substrate at a growth temperature lower than 1050 C. and growing an AlN spacer layer with a flow rate of NH.sub.3 at most 10% smaller than a summed flow rate of NH.sub.3 and H.sub.2. The grown GaN channel layer includes a substantial density of threading dislocations and the grown AlN layer includes a substantial density of pits.