The present application discloses a method for manufacturing a superjunction trench gate MOSFET, wherein after a top metal layer is fully etched off using a photomask for etching the top metal layer and a second mask layer, the second mask layer is not removed. Etching continues on exposed metal tungsten in a source region source contact to fully etch off the exposed metal tungsten in the source region source contact, followed by removing the second mask layer, and then a second dielectric layer is formed, not only reducing mask layers to reduce manufacturing costs, but also avoiding short circuits caused by connection of the exposed metal tungsten in the source region source contact to other conductors. The exposure of metal tungsten can be avoided in the case of saving one mask layer, and the process risk is reduced.

A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.

A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.

A multilayer structure with excellent crystallinity and a semiconductor device of the multilayer structure with good mobility are provided. A multilayer structure includes: a corundum structured crystal substrate; and a crystalline film containing a corundum structured crystalline oxide as a major component, the film formed directly on the substrate or with another layer therebetween, wherein the crystal substrate has an off angle from 0.2 to 12.0, and the crystalline oxide contains one or more metals selected from indium, aluminum, and gallium.

A process of forming a HEMT that makes the contract resistance of a non-rectifying electrode consistent with other device performance is disclosed. The process includes steps of growing a GaN channel layer with a thickness smaller than 600 nm on a SiC substrate at a growth temperature lower than 1050 C. and an AlN spacer layer with a flow rate of NH.sub.3 at most 10% smaller than a summed flow rate of NH.sub.3 and H.sub.2. The grown GaN channel layer includes substantial density of threading dislocations and the grown AlN layer includes substantial density of the pits.

The invention relates to a method for functionalizing an electrically conductive substrate, which is not a substrate made of gold, via a layer of chemical compounds, said method comprising the following steps: a step in which the electrically conductive substrate is placed in contact with chemical compounds comprising at least a disulfide terminal group; a step in which the disulfide terminal group of said chemical compounds is electro-oxidized, causing said chemical compounds to form a layer at the surface of the electrically conductive substrate.

A stacked semiconductor structure having a number of semiconductor diodes connected to one another in series, wherein each semiconductor diode has a p-n junction, and a tunnel diode is formed between sequential pairs of semiconductor diodes. The semiconductor diodes and the tunnel diodes jointly form a stack with a top and a bottom, and the number of semiconductor diodes is greater than or equal to two. When the stack is illuminated with light, at 300 K the stack has a source voltage of greater than 2 volts, and from the top of the stack to the bottom, a total thickness of the p and n absorption layers of a semiconductor diode increases from the topmost to the bottommost diode. The semiconductor diodes have substantially the same band gap, and the stack is formed on a substrate.

A method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor substrate from a surface of the semiconductor substrate. The insulation trench structure laterally surrounds a portion of the semiconductor substrate. The method further comprises modifying the laterally surrounded portion of the semiconductor substrate to form a vertical electrically conductive structure comprising an alloy material. The alloy material is an alloy of the semiconductor substrate material and at least one metal.

A method for forming a semiconductor device comprises forming an insulation trench structure comprising insulation material extending into the semiconductor substrate from a surface of the semiconductor substrate. The insulation trench structure laterally surrounds a portion of the semiconductor substrate. The method further comprises modifying the laterally surrounded portion of the semiconductor substrate to form a vertical electrically conductive structure comprising an alloy material. The alloy material is an alloy of the semiconductor substrate material and at least one metal.

Various methods and semiconductor structures for fabricating an FET device having Nickel atoms implanted in a silicide metal film on a source-drain contact region of the FET device thereby reducing resistance of the source-drain contact region of the FET device. An example fabrication method includes maskless blanket implantation of Nickel atoms across a semiconductor wafer. Nickel atoms can be implanted into silicide metal film of a source-drain contact region of nFET devices, pFET devices, or both, on a semiconductor wafer. Nickel atoms can be implanted into silicide metal film on a source-drain contact region of nFET devices and pFET devices. The silicide metal film on the source-drain contact region of the nFET device being a different material than the silicide metal film on the source-drain contact region of the pFET device.