Techniques for providing a high temperature soft mask for semiconductor devices are described. In an embodiment, spin coating semiconductor device components with organic planarization material having a defined aromatic content aromatic content to provide an organic planarization layer. The method can further comprise ultra-fast annealing the organic planarization layer and forming an implanted or doped region in the semiconductor device. Three-dimensional FinFET components of a device can be spin coated with organic planarization material having high aromatic content, with the device cured at a first temperature. The organic planarization layer can be ultra-fast annealed at a second temperature that is greater than the first temperature. Aspects can include patterning the device, and forming an implanted or doped region in a semiconductor device.

A pyrometer holder is mounted to an outer wall of a chamber while holding a lower radiation thermometer. The front end of the lower radiation thermometer is brought into abutment with a mounting portion of the pyrometer holder, and a bottom plate is brought into abutment with the rear end of the lower radiation thermometer. A tension spring is tensioned between the bottom plate and the mounting portion to prevent the lower radiation thermometer from falling off or misregistration. An angle adjusting mechanism adjusts the angle of the radiation thermometer with respect to the outer wall of the chamber, with the front end of the radiation thermometer serving as a supporting point. Thus, the measurement position of the lower radiation thermometer is adjusted.

A computer implemented method of monitoring a polishing process includes, for each sweep of a plurality of sweeps of an optical sensor across a substrate undergoing polishing, obtaining a plurality of current spectra, each current spectrum of the plurality of current spectra being a spectrum resulting from reflection of white light from the substrate, for each sweep of the plurality of sweeps, determining a difference between each current spectrum and each reference spectrum of a plurality of reference spectra to generate a plurality of differences, for each sweep of the plurality of sweeps, determining a smallest difference of the plurality of differences, thus generating a sequence of smallest difference, and determining a polishing endpoint based on the sequence of smallest differences.

Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.

A method includes receiving a semiconductor wafer into a chamber; generating a plasma within the chamber to accelerate particles toward the semiconductor wafer; generating a magnetic field above the semiconductor wafer by an electromagnetic structure contained within the chamber, wherein the electromagnetic structure comprises a plurality of electromagnetic elements; and adjusting the magnetic field, wherein the adjusting of the magnetic field includes moving positions of each of the plurality of electromagnetic elements independently.

A substrate processing device and a processing system process substrates each having a magnetic layer individually and are provided with: a support unit for supporting a substrate; a heating unit for heating the substrate supported on the support unit; a cooling unit for cooling the substrate supported on the support unit; a magnet unit for generating a magnetic field; and a processing chamber accommodating the support unit, the heating unit, and the cooling unit. The magnet unit includes a first and a second end surface which extend in parallel. The first and the second end surface are opposite to each other while being spaced apart from each other. The first end surface corresponds to a first magnetic pole of the magnet unit. The second end surface corresponds to a second magnetic pole of the magnet unit. The processing chamber is disposed between the first and the second end surface.

An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.

A processing temperature T.sub.S by a rapid thermal processing furnace is 1250 C. or more and 1350 C. or less, and a cooling rate R.sub.d from the processing temperature is in a range of 20 C./s or more and 150 C./s or less, and thermal processing is performed by adjusting the processing temperature T.sub.S and the cooling rate R.sub.d within a range between the upper limit P=0.00207T.sub.S.Math.R.sub.d2.52R.sub.d+13.3 (Formula (A)) and the lower limit P=0.000548T.sub.S.Math.R.sub.d0.605R.sub.d0.511 (Formula (B)) of an oxygen partial pressure P in a thermal processing atmosphere.

Embodiments of wafer bonding method and structures thereof are disclosed. The wafer bonding method can include performing a plasma activation treatment on a front surface of a first and a front surface of a second wafer; performing a silica sol treatment on the front surfaces of the first and the second wafers; performing a preliminary bonding process of the first and second wafer; and performing a heat treatment of the first and the second wafers to bond the front surface of the first wafer to the front surface of the second wafers.