A silicon carbide planar MOSFET includes a junction field-effect transistor (JFET) region that extends up to a top planar surface of the substrate. The JFET region includes a central area, which comprises a portion of the drift region that extends vertically to the top planar surface. First and second sidewall areas are disposed on opposite sides of the central area. The central area has a first lateral width and a first doping concentration. The first and second sidewall areas extend vertically to the top planar surface, with each having a second lateral width. The first and second sidewall areas each have a second doping concentration that is greater than the first doping concentration such that, at a zero bias condition, first and second depletion regions respectively extend only within the first and second sidewall areas of the JFET region.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.

An assembly present in an ion source for supporting an arc chamber upon a base plate includes a first arc support plate, a first screw, and a second screw. The first screw passes through a smooth through-hole in an arm of the first arc support plate and extends into a bore in the base plate. The second (or adjustable) screw passes through a threaded through-hole in an arm of the first arc support plate and engages an upper surface of the base plate itself, and can be used to change the altitude and angle of the first arc support plate relative to the base plate. This adjustment ability improves the beam quality of the ion source.

An assembly present in an ion source for supporting an arc chamber upon a base plate includes a first arc support plate, a first screw, and a second screw. The first screw passes through a smooth through-hole in an arm of the first arc support plate and extends into a bore in the base plate. The second (or adjustable) screw passes through a threaded through-hole in an arm of the first arc support plate and engages an upper surface of the base plate itself, and can be used to change the altitude and angle of the first arc support plate relative to the base plate. This adjustment ability improves the beam quality of the ion source.

A semiconductor device includes a substrate, a gate structure, a drift region, a source region, a drain region, and a doped region. The gate structure is above the substrate. The drift region is in the substrate and under the gate structure. The source region and the drain region are on opposite sides of the gate structure. The drain region is in the drift region, and the source region is outside the drift region. The doped region is in the drift region and between the drain region and the gate structure. The doped region is spaced apart from a bottom surface of the drain region.

A plurality of substrate support pins are erected on a susceptor that holds a semiconductor wafer that is an object being treated. The plurality of substrate support pins are set in a ring shape at equal intervals. A flash lamp irradiates the semiconductor wafer supported by the plurality of substrate support pins with flash light to heat the semiconductor wafer. The radius of a setting circle in which the plurality of substrate support pins are set is made larger as the pulse width of flash light emitted from the flash lamp decreases. To irradiate the semiconductor wafer with flash light while having the semiconductor wafer supported by the plurality of substrate support pins can prevent cracking of the semiconductor wafer despite possible abrupt deformation of the semiconductor wafer due to the flash-light irradiation.

A method for forming a semiconductor device includes providing a semiconductor substrate having an upper side and comprising, in a vertical cross-section substantially orthogonal to the upper side, a plurality of semiconductor mesas of a first monocrystalline semiconductor material which are spaced apart from each other by sacrificial layers selectively etchable with respect to the first monocrystalline semiconductor material and arranged in trenches extending from the upper side into the semiconductor substrate, forming on the semiconductor mesas a support structure mechanically connecting the semiconductor mesas, at least partly replacing the sacrificial layers while the semiconductor mesas remain mechanically connected via the support structure, and at least partly removing the support structure.

A semiconductor device having a substrate, a dielectric layer, a polycrystalline silicon (“poly”) resistor, a drain, and a source is disclosed. After implantation, the poly resistor may have a lateral doping profile with two peaks, one near each edge of the poly resistor, and a trough near the middle of the poly resistor. Such a doping profile can allow the poly resistor to have a resistance that is insensitive to small variations in critical dimension of the poly resistor. The resistance of the poly resistor may be determined by the doping dose of the tilted implant used to form the poly resistor. The tilted implant may be used to form the drain and the source of a transistor substantially simultaneously as forming the poly resistor.

An LDMOS transistor device may be provided, including a substrate having a conductivity region arranged therein, a first isolation structure arranged within the substrate, a source region and a drain region arranged within the conductivity region, a second isolation (local isolation) structure arranged between the source region and the drain region, and a gate structure arranged at least partially within the second isolation structure. The first isolation structure may extend along at least a portion of a border of the conductivity region, and a depth of the second isolation structure may be less than a depth of the first isolation structure. In use, a channel for electron flow may be formed along at least a part of a side of the gate structure arranged within the second isolation (local isolation) structure.

Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recombination region is located at least in the first type emitter regions and the third type emitter regions.